src/southbridge/intel/bd82x6x/early_thermal.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2014 Vladimir Serbinenko
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include "pch.h"
  19 #include "cpu/intel/model_206ax/model_206ax.h"
  20 #include <cpu/x86/msr.h>
  21
  22 static void write8p(uintptr_t addr, uint32_t val)
  23 {
  24         write8((u8 *)addr, val);
  25 }
  26
  27 static void write16p(uintptr_t addr, uint32_t val)
  28 {
  29         write16((u16 *)addr, val);
  30 }
  31
  32 static uint16_t read16p (uintptr_t addr)
  33 {
  34         return read16((u16 *)addr);
  35 }
  36
  37 /* Early thermal init, must be done prior to giving ME its memory
  38    which is done at the end of raminit.  */
  39 void early_thermal_init(void)
  40 {
  41         device_t dev;
  42         msr_t msr;
  43
  44         dev = PCI_DEV(0x0, 0x1f, 0x6);
  45
  46         /* Program address for temporary BAR.  */
  47         pci_write_config32(dev, 0x40, 0x40000000);
  48         pci_write_config32(dev, 0x44, 0x0);
  49
  50         /* Activate temporary BAR.  */
  51         pci_write_config32(dev, 0x40,
  52                            pci_read_config32(dev, 0x40) | 5);
  53
  54
  55         write16p (0x40000004, 0x3a2b);
  56         write8p (0x4000000c, 0xff);
  57         write8p (0x4000000d, 0x00);
  58         write8p (0x4000000e, 0x40);
  59         write8p (0x40000082, 0x00);
  60         write8p (0x40000001, 0xba);
  61
  62         /* Perform init.  */
  63         /* Configure TJmax.  */
  64         msr = rdmsr(MSR_TEMPERATURE_TARGET);
  65         write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
  66         /* Northbridge temperature slope and offset.  */
  67         write16p(0x40000016, 0x808c);
  68
  69         write16p (0x40000014, 0xde87);
  70
  71         /* Enable thermal data reporting, processor, PCH and northbridge.  */
  72         write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0);
  73
  74         /* Disable temporary BAR.  */
  75         pci_write_config32(dev, 0x40,
  76                            pci_read_config32(dev, 0x40) & ~1);
  77         pci_write_config32(dev, 0x40, 0);
  78
  79         write32 (DEFAULT_RCBA + 0x38b0,
  80                  (read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c);
  81 }