2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <timestamp.h>
19 #include <cpu/x86/tsc.h>
21 #include <arch/acpi.h>
22 #include <console/console.h>
24 uint64_t get_initial_timestamp(void)
27 .lo
= pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
28 .hi
= pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
30 return tsc_to_uint64(base_time
);
33 int southbridge_detect_s3_resume(void)
38 /* Check PM1_STS[15] to see if we are waking from Sx */
39 pm1_sts
= inw(DEFAULT_PMBASE
+ PM1_STS
);
41 /* Read PM1_CNT[12:10] to determine which Sx state */
42 pm1_cnt
= inl(DEFAULT_PMBASE
+ PM1_CNT
);
44 if ((pm1_sts
& WAK_STS
) && ((pm1_cnt
>> 10) & 7) == 5) {
45 if (acpi_s3_resume_allowed()) {
46 printk(BIOS_DEBUG
, "Resume from S3 detected.\n");
47 /* Clear SLP_TYPE. This will break stage2 but
48 * we care for that when we get there.
50 outl(pm1_cnt
& ~(7 << 10), DEFAULT_PMBASE
+ PM1_CNT
);
53 printk(BIOS_DEBUG
, "Resume from S3 detected, but disabled.\n");