2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 /* Intel 6/7 Series PCH PCIe support */
22 Method (IRQM, 1, Serialized) {
24 /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
25 Name (IQAA, Package() {
26 Package() { 0x0000ffff, 0, 0, 16 },
27 Package() { 0x0000ffff, 1, 0, 17 },
28 Package() { 0x0000ffff, 2, 0, 18 },
29 Package() { 0x0000ffff, 3, 0, 19 } })
30 Name (IQAP, Package() {
31 Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
32 Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
33 Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
34 Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } })
36 /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
37 Name (IQBA, Package() {
38 Package() { 0x0000ffff, 0, 0, 17 },
39 Package() { 0x0000ffff, 1, 0, 18 },
40 Package() { 0x0000ffff, 2, 0, 19 },
41 Package() { 0x0000ffff, 3, 0, 16 } })
42 Name (IQBP, Package() {
43 Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
44 Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
45 Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
46 Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } })
48 /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
49 Name (IQCA, Package() {
50 Package() { 0x0000ffff, 0, 0, 18 },
51 Package() { 0x0000ffff, 1, 0, 19 },
52 Package() { 0x0000ffff, 2, 0, 16 },
53 Package() { 0x0000ffff, 3, 0, 17 } })
54 Name (IQCP, Package() {
55 Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
56 Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
57 Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
58 Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } })
60 /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
61 Name (IQDA, Package() {
62 Package() { 0x0000ffff, 0, 0, 19 },
63 Package() { 0x0000ffff, 1, 0, 16 },
64 Package() { 0x0000ffff, 2, 0, 17 },
65 Package() { 0x0000ffff, 3, 0, 18 } })
66 Name (IQDP, Package() {
67 Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
68 Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
69 Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
70 Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } })
72 Switch (ToInteger (Arg0)) {
73 /* PCIe Root Port 1 and 5 */
74 Case (Package() { 1, 5 }) {
82 /* PCIe Root Port 2 and 6 */
83 Case (Package() { 2, 6 }) {
91 /* PCIe Root Port 3 and 7 */
92 Case (Package() { 3, 7 }) {
100 /* PCIe Root Port 4 and 8 */
101 Case (Package() { 4, 8 }) {
121 Name (_ADR, 0x001c0000)
123 #include "pcie_port.asl"
133 Name (_ADR, 0x001c0001)
135 #include "pcie_port.asl"
145 Name (_ADR, 0x001c0002)
147 #include "pcie_port.asl"
157 Name (_ADR, 0x001c0003)
159 #include "pcie_port.asl"
169 Name (_ADR, 0x001c0004)
171 #include "pcie_port.asl"
181 Name (_ADR, 0x001c0005)
183 #include "pcie_port.asl"
193 Name (_ADR, 0x001c0006)
195 #include "pcie_port.asl"
205 Name (_ADR, 0x001c0007)
207 #include "pcie_port.asl"