2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 /* PCI Interrupt Routing */
22 /* Onboard graphics (IGD) 0:2.0 */
23 Package() { 0x0002ffff, 0, 0, 16 },/* GFX INTA -> PIRQA (MSI) */
24 /* XHCI 0:14.0 (ivy only) */
25 Package() { 0x0014ffff, 0, 0, 19 },
26 /* High Definition Audio 0:1b.0 */
27 Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */
28 /* PCIe Root Ports 0:1c.x */
29 Package() { 0x001cffff, 0, 0, 17 },/* D28IP_P1IP PCIe INTA -> PIRQB */
30 Package() { 0x001cffff, 1, 0, 21 },/* D28IP_P2IP PCIe INTB -> PIRQF */
31 Package() { 0x001cffff, 2, 0, 19 },/* D28IP_P3IP PCIe INTC -> PIRQD */
32 Package() { 0x001cffff, 3, 0, 20 },/* D28IP_P3IP PCIe INTD -> PIRQE */
34 Package() { 0x001dffff, 0, 0, 19 },/* D29IP_E1P EHCI1 INTA -> PIRQD */
36 Package() { 0x001affff, 0, 0, 21 },/* D26IP_E2P EHCI2 INTA -> PIRQF */
37 /* LPC devices 0:1f.0 */
38 Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */
39 Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */
40 Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */
41 Package() { 0x001fffff, 3, 0, 18 },
45 /* Onboard graphics (IGD) 0:2.0 */
46 Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
47 /* XHCI 0:14.0 (ivy only) */
48 Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
49 /* High Definition Audio 0:1b.0 */
50 Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
51 /* PCIe Root Ports 0:1c.x */
52 Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
53 Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
54 Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
55 Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
57 Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
59 Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
60 /* LPC device 0:1f.0 */
61 Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
62 Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
63 Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
64 Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },