2 * This file is part of the coreboot project.
4 * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
5 * Copyright (C) 2009 Advanced Micro Devices, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
19 Name(HPBA, 0xFED00000) /* Base address of HPET table */
21 /* PIC IRQ mapping registers, C00h-C01h */
22 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
23 Field(PRQM, ByteAcc, NoLock, Preserve) {
25 PRQD, 0x00000008, /* Offset: 1h */
27 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
28 PINA, 0x00000008, /* Index 0 */
29 PINB, 0x00000008, /* Index 1 */
30 PINC, 0x00000008, /* Index 2 */
31 PIND, 0x00000008, /* Index 3 */
32 AINT, 0x00000008, /* Index 4 */
33 SINT, 0x00000008, /* Index 5 */
34 , 0x00000008, /* Index 6 */
35 AAUD, 0x00000008, /* Index 7 */
36 AMOD, 0x00000008, /* Index 8 */
37 PINE, 0x00000008, /* Index 9 */
38 PINF, 0x00000008, /* Index A */
39 PING, 0x00000008, /* Index B */
40 PINH, 0x00000008, /* Index C */
43 /* PCI Error control register */
44 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
45 Field(PERC, ByteAcc, NoLock, Preserve) {
53 /* PCIe Configuration Space for 16 busses */
54 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
55 Field(PCFG, ByteAcc, NoLock, Preserve) {
56 /* Byte offsets are computed using the following technique:
57 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
58 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
60 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
62 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
73 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
76 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
78 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
80 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
82 P92E, 1, /* Port92 decode enable */
85 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
86 Field(SB5, AnyAcc, NoLock, Preserve){
88 Offset(0x120), /* Port 0 Task file status */
94 Offset(0x128), /* Port 0 Serial ATA status */
98 Offset(0x12C), /* Port 0 Serial ATA control */
100 Offset(0x130), /* Port 0 Serial ATA error */
105 offset(0x1A0), /* Port 1 Task file status */
111 Offset(0x1A8), /* Port 1 Serial ATA status */
115 Offset(0x1AC), /* Port 1 Serial ATA control */
117 Offset(0x1B0), /* Port 1 Serial ATA error */
122 Offset(0x220), /* Port 2 Task file status */
128 Offset(0x228), /* Port 2 Serial ATA status */
132 Offset(0x22C), /* Port 2 Serial ATA control */
134 Offset(0x230), /* Port 2 Serial ATA error */
139 Offset(0x2A0), /* Port 3 Task file status */
145 Offset(0x2A8), /* Port 3 Serial ATA status */
149 Offset(0x2AC), /* Port 3 Serial ATA control */
151 Offset(0x2B0), /* Port 3 Serial ATA error */
156 Method(CIRQ, 0x00, NotSerialized){
167 /* set "A", 8259 interrupts */
168 Name (PRSA, ResourceTemplate () {
169 IRQ(Level, ActiveLow, Exclusive) {4, 7, 10, 11, 12, 14, 15}
172 Method (CRSA, 1, Serialized) {
173 Name (LRTL, ResourceTemplate() {
174 IRQ(Level, ActiveLow, Shared) {15}
176 CreateWordField(LRTL, 1, LIRQ)
177 ShiftLeft(1, Arg0, LIRQ)
181 Method (SRSA, 1, Serialized) {
182 CreateWordField(Arg0, 1, LIRQ)
183 FindSetRightBit(LIRQ, Local0)
191 Name(_HID, EISAID("PNP0C0F"))
195 Return(0x0B) /* LNKA is invisible */
197 Return(0x09) /* LNKA is disabled */
206 Method (_CRS, 0, Serialized) {
209 Method (_SRS, 1, Serialized) {
210 Store (SRSA(Arg0), PINA)
215 Name(_HID, EISAID("PNP0C0F"))
219 Return(0x0B) /* LNKB is invisible */
221 Return(0x09) /* LNKB is disabled */
230 Method (_CRS, 0, Serialized) {
233 Method (_SRS, 1, Serialized) {
234 Store (SRSA(Arg0), PINB)
239 Name(_HID, EISAID("PNP0C0F"))
243 Return(0x0B) /* LNKC is invisible */
245 Return(0x09) /* LNKC is disabled */
254 Method (_CRS, 0, Serialized) {
257 Method (_SRS, 1, Serialized) {
258 Store (SRSA(Arg0), PINC)
263 Name(_HID, EISAID("PNP0C0F"))
267 Return(0x0B) /* LNKD is invisible */
269 Return(0x09) /* LNKD is disabled */
278 Method (_CRS, 0, Serialized) {
281 Method (_SRS, 1, Serialized) {
282 Store (SRSA(Arg0), PIND)
287 Name(_HID, EISAID("PNP0C0F"))
291 Return(0x0B) /* LNKE is invisible */
293 Return(0x09) /* LNKE is disabled */
302 Method (_CRS, 0, Serialized) {
305 Method (_SRS, 1, Serialized) {
306 Store (SRSA(Arg0), PINE)
311 Name(_HID, EISAID("PNP0C0F"))
315 Return(0x0B) /* LNKF is invisible */
317 Return(0x09) /* LNKF is disabled */
326 Method (_CRS, 0, Serialized) {
329 Method (_SRS, 1, Serialized) {
330 Store (SRSA(Arg0), PINF)
335 Name(_HID, EISAID("PNP0C0F"))
339 Return(0x0B) /* LNKG is invisible */
341 Return(0x09) /* LNKG is disabled */
350 Method (_CRS, 0, Serialized) {
353 Method (_SRS, 1, Serialized) {
354 Store (SRSA(Arg0), PING)
359 Name(_HID, EISAID("PNP0C0F"))
363 Return(0x0B) /* LNKH is invisible */
365 Return(0x09) /* LNKH is disabled */
374 Method (_CRS, 0, Serialized) {
377 Method (_SRS, 1, Serialized) {
378 Store (SRSA(Arg0), PINH)
382 } /* End Scope(_SB) */