src/southbridge/amd/sb700/reset.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 - 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 // Use simple device model for this file even in ramstage
  17 #define __SIMPLE_DEVICE__
  18
  19 #include <arch/io.h>
  20 #include <reset.h>
  21
  22 #define HT_INIT_CONTROL         0x6C
  23 #define HTIC_BIOSR_Detect       (1<<5)
  24
  25 #if CONFIG_MAX_PHYSICAL_CPUS > 32
  26 #define NODE_PCI(x, fn)        ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
  27 #else
  28 #define NODE_PCI(x, fn)        PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
  29 #endif
  30
  31 static void set_bios_reset(void)
  32 {
  33         u32 nodes;
  34         u32 htic;
  35         pci_devfn_t dev;
  36         int i;
  37
  38         nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
  39         for(i = 0; i < nodes; i++) {
  40                 dev = NODE_PCI(i, 0);
  41                 htic = pci_read_config32(dev, HT_INIT_CONTROL);
  42                 htic &= ~HTIC_BIOSR_Detect;
  43                 pci_write_config32(dev, HT_INIT_CONTROL, htic);
  44         }
  45 }
  46
  47 void hard_reset(void)
  48 {
  49         set_bios_reset();
  50
  51         /* Try rebooting through port 0xcf9 */
  52         /* Actually it is not a real hard_reset
  53          * --- it only reset coherent link table, but not reset link freq and width
  54          */
  55         outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
  56         outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
  57 }
  58
  59 void soft_reset(void)
  60 {
  61         set_bios_reset();
  62         /* link reset */
  63         outb(0x06, 0x0cf9);
  64 }