src/southbridge/amd/sb600/pci.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <device/device.h>
  18 #include <device/pci.h>
  19 #include <device/pci_ids.h>
  20 #include <device/pci_ops.h>
  21 #include "sb600.h"
  22
  23 static void pci_init(struct device *dev)
  24 {
  25         u32 dword;
  26         u16 word;
  27         u8 byte;
  28
  29         /* RPR 4.1 Enables the PCI-bridge subtractive decode */
  30         /* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
  31         byte = pci_read_config8(dev, 0x4B);
  32         byte |= 1 << 7;
  33         pci_write_config8(dev, 0x4B, byte);
  34         byte = pci_read_config8(dev, 0x40);
  35         byte |= 1 << 5;
  36         pci_write_config8(dev, 0x40, byte);
  37
  38         /* RPR4.2 PCI-bridge upstream dual address window */
  39         /* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
  40         byte = pci_read_config8(dev, 0x50);
  41         byte |= 1 << 0;
  42         pci_write_config8(dev, 0x50, byte);
  43
  44         /* RPR 4.3 PCI bus 64-byte DMA read access */
  45         /* Enhance the PCI bus DMA performance */
  46         byte = pci_read_config8(dev, 0x4B);
  47         byte |= 1 << 4;
  48         pci_write_config8(dev, 0x4B, byte);
  49
  50         /* RPR 4.4 Enables the PCIB writes to be cacheline aligned. */
  51         /* The size of the writes will be set in the Cacheline Register */
  52         byte = pci_read_config8(dev, 0x40);
  53         byte |= 1 << 1;
  54         pci_write_config8(dev, 0x40, byte);
  55
  56         /* RPR 4.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
  57         pci_write_config8(dev, 0x0D, 0x40);
  58         pci_write_config8(dev, 0x1B, 0x40);
  59
  60         /* RPR 4.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
  61         byte = pci_read_config8(dev, 0x4B);
  62         byte |= 1 << 6;
  63         pci_write_config8(dev, 0x4B, byte);
  64
  65         /* RPR 4.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
  66         byte = pci_read_config8(dev, 0x4B);
  67         byte |= 1 << 0;
  68         pci_write_config8(dev, 0x4B, byte);
  69
  70         /* RPR 4.8 Adjusts the GNT# de-assertion time */
  71         word = pci_read_config16(dev, 0x64);
  72         word |= 1 << 12;
  73         pci_write_config16(dev, 0x64, word);
  74
  75         /* RPR 4.9 Fast Back to Back transactions support */
  76         byte = pci_read_config8(dev, 0x48);
  77         byte |= 1 << 2;
  78         pci_write_config8(dev, 0x48, byte);
  79
  80         /* RPR 4.10 Enable Lock Operation */
  81         byte = pci_read_config8(dev, 0x48);
  82         byte |= 1 << 3;
  83         pci_write_config8(dev, 0x48, byte);
  84         byte = pci_read_config8(dev, 0x40);
  85         byte |= (1 << 2);
  86         pci_write_config8(dev, 0x40, byte);
  87
  88         /* RPR 4.11 Enable additional optional PCI clock */
  89         word = pci_read_config16(dev, 0x64);
  90         word |= 1 << 8;
  91         pci_write_config16(dev, 0x64, word);
  92
  93         /* rpr4.12 Disable Fewer-Retry Mode for A11-A13 only. 0x64[5:4] clear */
  94         byte = pci_read_config8(dev, 0x64);
  95         byte &= 0xcf;
  96         pci_write_config8(dev, 0x64, byte);
  97
  98         /* rpr4.14 Disabling Downstream Flush, for A12 only, 0x64[18]. */
  99         dword = pci_read_config32(dev, 0x64);
 100         dword |= (1 << 18);
 101         pci_write_config32(dev, 0x64, dword);
 102
 103         /* RPR 4.13 Enable One-Prefetch-Channel Mode */
 104         dword = pci_read_config32(dev, 0x64);
 105         dword |= 1 << 20;
 106         pci_write_config32(dev, 0x64, dword);
 107
 108         /* RPR 4.15 Disable PCIB MSI Capability */
 109         byte = pci_read_config8(dev, 0x40);
 110         byte &= ~(1 << 3);
 111         pci_write_config8(dev, 0x40, byte);
 112
 113         /* rpr4.16 Adjusting CLKRUN# */
 114         dword = pci_read_config32(dev, 0x64);
 115         dword |= (1 << 15);
 116         pci_write_config32(dev, 0x64, dword);
 117 }
 118
 119 static struct pci_operations lops_pci = {
 120         .set_subsystem = 0,
 121 };
 122
 123 static struct device_operations pci_ops = {
 124         .read_resources = pci_bus_read_resources,
 125         .set_resources = pci_dev_set_resources,
 126         .enable_resources = pci_bus_enable_resources,
 127         .init = pci_init,
 128         .scan_bus = pci_scan_bridge,
 129         /* .enable           = sb600_enable, */
 130         .reset_bus = pci_bus_reset,
 131         .ops_pci = &lops_pci,
 132 };
 133
 134 static const struct pci_driver pci_driver __pci_driver = {
 135         .ops = &pci_ops,
 136         .vendor = PCI_VENDOR_ID_ATI,
 137         .device = PCI_DEVICE_ID_ATI_SB600_PCI,
 138 };