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tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / southbridge / amd / rs780 / early_setup.c
blobca8d79a904b146fe0fc045cf824c6c06755e5d2e
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include "rev.h"
17
18 #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
19 #define NBMISC_INDEX 0x60
20 #define NBMC_INDEX 0xE8
21
22 static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
23 {
24 pci_write_config32(dev, index_reg, index);
25 return pci_read_config32(dev, index_reg + 0x4);
26 }
27
28 static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
29 {
30 pci_write_config32(dev, index_reg, index /* | 0x80 */ );
31 pci_write_config32(dev, index_reg + 0x4, data);
32 }
33
34 static u32 nbmisc_read_index(device_t nb_dev, u32 index)
35 {
36 return nb_read_index((nb_dev), NBMISC_INDEX, (index));
37 }
38
39 static void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
40 {
41 nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
42 }
43
44 static u32 htiu_read_index(device_t nb_dev, u32 index)
45 {
46 return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
47 }
48
49 static void htiu_write_index(device_t nb_dev, u32 index, u32 data)
50 {
51 nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
52 }
53
54 static u32 nbmc_read_index(device_t nb_dev, u32 index)
55 {
56 return nb_read_index((nb_dev), NBMC_INDEX, (index));
57 }
58
59 static void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
60 {
61 nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
62 }
63
64 static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
65 u32 val)
66 {
67 u32 reg_old, reg;
68 reg = reg_old = htiu_read_index(nb_dev, reg_pos);
69 reg &= ~mask;
70 reg |= val;
71 if (reg != reg_old) {
72 htiu_write_index(nb_dev, reg_pos, reg);
73 }
74 }
75
76 static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
77 u32 val)
78 {
79 u32 reg_old, reg;
80 reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
81 reg &= ~mask;
82 reg |= val;
83 if (reg != reg_old) {
84 nbmisc_write_index(nb_dev, reg_pos, reg);
85 }
86 }
87
88 static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
89 u32 val)
90 {
91 u32 reg_old, reg;
92 reg = reg_old = pci_read_config32(nb_dev, reg_pos);
93 reg &= ~mask;
94 reg |= val;
95 if (reg != reg_old) {
96 pci_write_config32(nb_dev, reg_pos, reg);
97 }
98 }
99 /* family 10 only, for reg > 0xFF */
100 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
101 static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
102 u32 val)
103 {
104 u32 reg_old, reg;
105 reg = reg_old = Get_NB32(fam10_dev, reg_pos);
106 reg &= ~mask;
107 reg |= val;
108 if (reg != reg_old) {
109 Set_NB32(fam10_dev, reg_pos, reg);
110 }
111 }
112 #else
113 #define set_fam10_ext_cfg_enable_bits(a, b, c, d) do {} while (0)
114 #endif
115
116
117 static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
118 u8 val)
119 {
120 u8 reg_old, reg;
121 reg = reg_old = pci_read_config8(nb_dev, reg_pos);
122 reg &= ~mask;
123 reg |= val;
124 if (reg != reg_old) {
125 pci_write_config8(nb_dev, reg_pos, reg);
126 }
127 }
128
129 static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
130 u32 val)
131 {
132 u32 reg_old, reg;
133 reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
134 reg &= ~mask;
135 reg |= val;
136 if (reg != reg_old) {
137 nbmc_write_index(nb_dev, reg_pos, reg);
138 }
139 }
140
141 static u8 is_famly10(void)
142 {
143 return (cpuid_eax(1) & 0xff00000) != 0;
144 }
145
146 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
147 static u8 l3_cache(void)
148 {
149 return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
150 }
151
152 static u8 cpu_core_number(void)
153 {
154 return (cpuid_ecx(0x80000008) & 0xFF) + 1;
155 }
156 #endif
157
158 static u8 get_nb_rev(device_t nb_dev)
159 {
160 u8 reg;
161 reg = pci_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */
162 switch(reg & 3)
163 {
164 case 0x01:
165 reg = REV_RS780_A12;
166 break;
167 case 0x02:
168 reg = REV_RS780_A13;
169 break;
170 default:
171 reg = REV_RS780_A11;
172 break;
173 }
174 return reg;
175 }
176
177 /*****************************************
178 * Init HT link speed/width for rs780 -- k8 link
179 * 1: Check CPU Family, Family10?
180 * 2: Get CPU's HT speed and width
181 * 3: Decide HT mode 1 or 3 by HT Speed. >1GHz: HT3, else HT1
182 *****************************************/
183 static const u8 rs780_ibias[] = {
184 /* 1, 3 are reserved. */
185 [0x0] = 0x4C, /* 200MHz HyperTransport 1 only */
186 [0x2] = 0x4C, /* 400MHz HyperTransport 1 only */
187 [0x4] = 0xB6, /* 600MHz HyperTransport 1 only */
188 [0x5] = 0x4C, /* 800MHz HyperTransport 1 only */
189 [0x6] = 0x9D, /* 1GHz HyperTransport 1 only */
190 /* HT3 for Family 10 */
191 [0x7] = 0xB6, /* 1.2GHz HyperTransport 3 only */
192 [0x8] = 0x2B, /* 1.4GHz HyperTransport 3 only */
193 [0x9] = 0x4C, /* 1.6GHz HyperTransport 3 only */
194 [0xa] = 0x6C, /* 1.8GHz HyperTransport 3 only */
195 [0xb] = 0x9D, /* 2.0GHz HyperTransport 3 only */
196 [0xc] = 0xAD, /* 2.2GHz HyperTransport 3 only */
197 [0xd] = 0xB6, /* 2.4GHz HyperTransport 3 only */
198 [0xe] = 0xC6, /* 2.6GHz HyperTransport 3 only */
199 };
200
201 static void rs780_htinit(void)
202 {
203 /*
204 * About HT, it has been done in enumerate_ht_chain().
205 */
206 device_t cpu_f0, rs780_f0, clk_f1;
207 u32 reg;
208 u8 cpu_ht_freq, ibias;
209
210 cpu_f0 = PCI_DEV(0, 0x18, 0);
211 /************************
212 * get cpu's ht freq, in cpu's function 0, offset 0x88
213 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
214 * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
215 * value to this reg, and that value takes effect on the next warm reset or
216 * LDTSTOP_L disconnect sequence.
217 * please see the table rs780_ibias about the value and its corresponding frequency.
218 ************************/
219 reg = pci_read_config32(cpu_f0, 0x88);
220 cpu_ht_freq = (reg & 0xf00) >> 8;
221 printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq);
222 rs780_f0 = PCI_DEV(0, 0, 0);
223 //set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28);
224
225 clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */
226
227 ibias = rs780_ibias[cpu_ht_freq];
228
229 /* If HT freq>1GHz, we assume the CPU is fam10, else it is K8.
230 * Is it appropriate?
231 * Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases.
232 * So we check 6 only, it would be faster. */
233 if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) ||
234 (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) {
235 printk(BIOS_INFO, "rs780_htinit: HT1 mode\n");
236
237 /* HT1 mode, RPR 8.4.2 */
238 /* set IBIAS code */
239 set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
240 /* Optimizes chipset HT transmitter drive strength */
241 set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
242 } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
243 printk(BIOS_INFO, "rs780_htinit: HT3 mode\n");
244
245 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
246 /* HT3 mode, RPR 8.4.3 */
247 set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);
248
249 /* set IBIAS code */
250 set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
251 /* Optimizes chipset HT transmitter drive strength */
252 set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
253 /* Enables error-retry mode */
254 set_nbcfg_enable_bits(rs780_f0, 0x44, 0x1, 0x1);
255 /* Enables scrambling and Disables command throttling */
256 set_nbcfg_enable_bits(rs780_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14));
257 /* Enables transmitter de-emphasis */
258 set_nbcfg_enable_bits(rs780_f0, 0xa4, 1 << 31, 1 << 31);
259 /* Enables transmitter de-emphasis level */
260 /* Sets training 0 time */
261 set_nbcfg_enable_bits(rs780_f0, 0xa0, 0x3F, 0x14);
262
263 /* Enables strict TM4 detection */
264 set_htiu_enable_bits(rs780_f0, 0x15, 0x1 << 22, 0x1 << 22);
265 /* Enables proper DLL reset sequence */
266 set_htiu_enable_bits(rs780_f0, 0x16, 0x1 << 10, 0x1 << 10);
267
268 /* HyperTransport 3 Processor register settings to be done in northbridge */
269 /* Enables error-retry mode */
270 set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130, 1 << 0, 1 << 0);
271 /* Enables scrambling */
272 set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170, 1 << 3, 1 << 3);
273 /* Enables transmitter de-emphasis
274 * This depends on the PCB design and the trace */
275 /* TODO: */
276 /* Disables command throttling */
277 set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10);
278 /* Sets Training 0 Time. See T0Time table for encodings */
279 set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20);
280 /* TODO: */
281 #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
282 }
283 }
284
285 #if !CONFIG_NORTHBRIDGE_AMD_AMDFAM10
286 /*******************************************************
287 * Optimize k8 with UMA.
288 * See BKDG_NPT_0F guide for details.
289 * The processor node is addressed by its Node ID on the HT link and can be
290 * accessed with a device number in the PCI configuration space on Bus0.
291 * The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
292 * to Device 25, and so on.
293 * The processor implements configuration registers in PCI configuration
294 * space using the following four headers
295 * Function0: HT technology configuration
296 * Function1: Address map configuration
297 * Function2: DRAM and HT technology Trace mode configuration
298 * Function3: Miscellaneous configuration
299 *******************************************************/
300 static void k8_optimization(void)
301 {
302 device_t k8_f0, k8_f2, k8_f3;
303 msr_t msr;
304
305 printk(BIOS_INFO, "k8_optimization()\n");
306 k8_f0 = PCI_DEV(0, 0x18, 0);
307 k8_f2 = PCI_DEV(0, 0x18, 2);
308 k8_f3 = PCI_DEV(0, 0x18, 3);
309
310 /* 8.6.6 K8 Buffer Allocation Settings */
311 pci_write_config32(k8_f0, 0x90, 0x01700169); /* CIM NPT_Optimization */
312 set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
313 set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 26, 3 << 26);
314 set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
315 /* set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); */ /* TODO */
316
317 pci_write_config32(k8_f3, 0x70, 0x51220111);
318 pci_write_config32(k8_f3, 0x74, 0x50404021);
319 pci_write_config32(k8_f3, 0x78, 0x08002A00);
320 if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12)
321 pci_write_config32(k8_f3, 0x7C, 0x0000211A); /* dual core */
322 else
323 pci_write_config32(k8_f3, 0x7C, 0x0000212B); /* single core */
324 set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
325
326 set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
327 set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
328 set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 0 << 10);
329 set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
330 set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
331
332 msr = rdmsr(0xC001001F);
333 msr.lo &= ~(1 << 9);
334 msr.hi &= ~(1 << 4);
335 wrmsr(0xC001001F, msr);
336 }
337 #else
338 #define k8_optimization() do{}while(0)
339 #endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
340
341 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
342 static void fam10_optimization(void)
343 {
344 device_t cpu_f0, cpu_f2, cpu_f3;
345 u32 val;
346
347 printk(BIOS_INFO, "fam10_optimization()\n");
348
349 cpu_f0 = PCI_DEV(0, 0x18, 0);
350 cpu_f2 = PCI_DEV(0, 0x18, 2);
351 cpu_f3 = PCI_DEV(0, 0x18, 3);
352
353 /* 8.6.4.1 */
354 /* Table 8-13 */
355 pci_write_config32(cpu_f0, 0x90, 0x808502D0);
356 /* Table 8-14 */
357 pci_write_config32(cpu_f0, 0x94, 0x00000000);
358
359 /* Table 8-15 */
360 val = pci_read_config32(cpu_f0, 0x68);
361 val |= 1 << 24;
362 pci_write_config32(cpu_f0, 0x68, val);
363
364 /* Table 8-16 */
365 val = pci_read_config32(cpu_f0, 0x84);
366 val &= ~(1 << 12);
367 pci_write_config32(cpu_f0, 0x84, val);
368
369 /* Table 8-17 */
370 val = pci_read_config32(cpu_f2, 0x90);
371 val &= ~(1 << 10);
372 pci_write_config32(cpu_f2, 0x90, val);
373
374 /* Table 8-18 */
375 pci_write_config32(cpu_f3, 0x6C, 0x60018051);
376 /* Table 8-19 */
377 pci_write_config32(cpu_f3, 0x70, 0x60321151);
378 /* Table 8-20 */
379 pci_write_config32(cpu_f3, 0x74, 0x00980101);
380 /* Table 8-21 */
381 pci_write_config32(cpu_f3, 0x78, 0x00200C14);
382 /* Table 8-22 */
383 pci_write_config32(cpu_f3, 0x7C, 0x00070811); /* TODO: Check if L3 Cache is enabled. */
384
385 /* Table 8-23 */
386 Set_NB32(cpu_f3, 0x140, 0x00D33656);
387 /* Table 8-24 */
388 Set_NB32(cpu_f3, 0x144, 0x00000036);
389 /* Table 8-25 */
390 Set_NB32(cpu_f3, 0x148, 0x8000832A);
391 /* Table 8-26 */
392 Set_NB32(cpu_f3, 0x158, 0);
393 /* L3 Disabled: L3 Enabled: */
394 /* cores: 2 3 4 2 3 4 */
395 /* bit8:4 28 26 24 24 20 16 */
396 if (!l3_cache()) {
397 Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (24 + 2*(4-cpu_core_number())) << 4 | 2);
398 } else {
399 Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (16 + 4*(4-cpu_core_number())) << 4 | 4);
400 }
401 }
402 #else
403 #define fam10_optimization() do{}while(0)
404 #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
405
406 /*****************************************
407 * rs780_por_pcicfg_init()
408 *****************************************/
409 static void rs780_por_pcicfg_init(device_t nb_dev)
410 {
411 /* enable PCI Memory Access */
412 set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02);
413 /* Set RCRB Enable */
414 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x1);
415 /* allow decode of 640k-1MB */
416 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xEF), 0x10);
417 /* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */
418 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x4);
419 /* Power Management Register Enable */
420 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80);
421
422 /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
423 * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
424 * BMMsgEn */
425 set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1);
426
427 /* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
428 * Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */
429 set_nbcfg_enable_bits_8(nb_dev, 0x4E, (u8)(~0xFF), 0x05);
430 /* Reg94h[4:0] = 0x0 P drive strength offset 0
431 * Reg94h[6:5] = 0x2 P drive strength additive adjust */
432 set_nbcfg_enable_bits_8(nb_dev, 0x94, (u8)(~0x80), 0x40);
433
434 /* Reg94h[20:16] = 0x0 N drive strength offset 0
435 * Reg94h[22:21] = 0x2 N drive strength additive adjust */
436 set_nbcfg_enable_bits_8(nb_dev, 0x96, (u8)(~0x80), 0x40);
437
438 /* Reg80h[4:0] = 0x0 Termination offset
439 * Reg80h[6:5] = 0x2 Termination additive adjust */
440 set_nbcfg_enable_bits_8(nb_dev, 0x80, (u8)(~0x80), 0x40);
441
442 /* Reg80h[14] = 0x1 Enable receiver termination control */
443 set_nbcfg_enable_bits_8(nb_dev, 0x81, (u8)(~0xFF), 0x40);
444
445 /* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on
446 * Reg94h[14] = 0x1 Enable drive strength control */
447 set_nbcfg_enable_bits_8(nb_dev, 0x95, (u8)(~0x3F), 0xC4);
448
449 /* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */
450 set_nbcfg_enable_bits_8(nb_dev, 0x97, (u8)(~0x1F), 0xE0);
451
452 /* Reg8Ch[9] enables Gfx Debug BAR programming
453 * Reg8Ch[10] enables Gfx Debug BAR operation
454 * Enable programming of the debug bar now, but enable
455 * operation only after it has been programmed */
456 set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x02);
457 }
458
459 static void rs780_por_mc_index_init(device_t nb_dev)
460 {
461 set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F);
462 set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060);
463 set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060);
464 set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000);
465 set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000);
466 set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E);
467 set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E);
468 }
469
470 static void rs780_por_misc_index_init(device_t nb_dev)
471 {
472 /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
473 * Block non-snoop DMA request if PMArbDis is set.
474 * Set BMSetDis */
475 set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180);
476 set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040);
477
478 /* NBCFG (NBMISCIND 0x0): NB_CNTL -
479 * HIDE_NB_AGP_CAP ([0], default=1)HIDE
480 * HIDE_P2P_AGP_CAP ([1], default=1)HIDE
481 * HIDE_NB_GART_BAR ([2], default=1)HIDE
482 * AGPMODE30 ([4], default=0)DISABLE
483 * AGP30ENCHANCED ([5], default=0)DISABLE
484 * HIDE_AGP_CAP ([8], default=1)ENABLE */
485 set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */
486
487 /* NBMISCIND:0x6A[16]= 1 SB link can get a full swing
488 * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000);
489 * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */
490 set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000);
491
492 /* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */
493 set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500);
494
495 /* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */
496 set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000);
497
498 /* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */
499 set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008);
500
501 /*
502 * Enable access to DEV8
503 * Enable setPower message for all ports
504 */
505 set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6);
506 set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20);
507 set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20);
508 set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20);
509 set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20);
510 set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20);
511 set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20);
512 set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20);
513 set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20, 1 << 20);
514 set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20, 1 << 20);
515
516 set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
517 set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30);
518
519 set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x48);
520 /* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */
521 set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180);
522 }
523
524 /*****************************************
525 * Some setting is from rpr. Some is from CIMx.
526 *****************************************/
527 static void rs780_por_htiu_index_init(device_t nb_dev)
528 {
529 #if 0 /* get from rpr. */
530 set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17);
531 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<0, 0x0<<0);
532 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<1, 0x1<<1);
533 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<9, 0x1<<9);
534 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<13, 0x1<<13);
535 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<17, 0x1<<17);
536 set_htiu_enable_bits(nb_dev, 0x06, 0x3<<15, 0x3<<15);
537 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<25, 0x1<<25);
538 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<30, 0x1<<30);
539
540 set_htiu_enable_bits(nb_dev, 0x07, 0x1<<0, 0x1<<0);
541 set_htiu_enable_bits(nb_dev, 0x07, 0x1<<1, 0x0<<1);
542 set_htiu_enable_bits(nb_dev, 0x07, 0x1<<2, 0x0<<2);
543 set_htiu_enable_bits(nb_dev, 0x07, 0x1<<15, 0x1<<15);
544
545 set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<0, 0x1<<0);
546 set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<2, 0x2<<2);
547 set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<4, 0x0<<4);
548
549 /* A12 only */
550 set_htiu_enable_bits(nb_dev, 0x2D, 0x1<<4, 0x1<<4);
551 set_htiu_enable_bits(nb_dev, 0x2D, 0x1<<6, 0x1<<6);
552 set_htiu_enable_bits(nb_dev, 0x05, 0x1<<2, 0x1<<2);
553
554 set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF);
555 #else /* get from CIM. It is more reliable than above. */
556 set_htiu_enable_bits(nb_dev, 0x05, (1<<10|1<<9), 1<<10 | 1<<9);
557 set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x04203A202);
558
559 set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x8001/* | 7 << 8 */); /* fam 10 */
560
561 set_htiu_enable_bits(nb_dev, 0x15, ~0xFFFFFFFF, 1<<31| 1<<30 | 1<<27);
562 set_htiu_enable_bits(nb_dev, 0x1C, ~0xFFFFFFFF, 0xFFFE0000);
563
564 set_htiu_enable_bits(nb_dev, 0x4B, (1<<11), 1<<11);
565
566 set_htiu_enable_bits(nb_dev, 0x0C, ~0xFFFFFFC0, 1<<0|1<<3);
567
568 set_htiu_enable_bits(nb_dev, 0x17, (1<<27|1<<1), 0x1<<1);
569 set_htiu_enable_bits(nb_dev, 0x17, 0x1 << 30, 0x1<<30);
570
571 set_htiu_enable_bits(nb_dev, 0x19, (0xFFFFF+(1<<31)), 0x186A0+(1<<31));
572
573 set_htiu_enable_bits(nb_dev, 0x16, (0x3F<<10), 0x7<<10);
574
575 set_htiu_enable_bits(nb_dev, 0x23, 0xFFFFFFF, 1<<28);
576
577 set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF);
578 #endif
579 }
580
581 /*****************************************
582 * Configure RS780 registers to power-on default RPR.
583 * POR: Power On Reset
584 * RPR: Register Programming Requirements
585 *****************************************/
586 static void rs780_por_init(device_t nb_dev)
587 {
588 printk(BIOS_INFO, "rs780_por_init\n");
589 /* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */
590 rs780_por_pcicfg_init(nb_dev);
591
592 /* ATINB_MCIND_POR_TABLE */
593 rs780_por_mc_index_init(nb_dev);
594
595 /* ATINB_MISCIND_POR_TABLE */
596 rs780_por_misc_index_init(nb_dev);
597
598 /* ATINB_HTIUNBIND_POR_TABLE */
599 rs780_por_htiu_index_init(nb_dev);
600
601 /* ATINB_CLKCFG_PORT_TABLE */
602 /* rs780 A11 SB Link full swing? */
603
604 /* SET NB_MISC_REG01 BIT8 to Enable HDMI, reference CIMX_5_9_3 NBPOR_InitPOR(),
605 * then the accesses to internal graphics IO space 0x60/0x64, are forwarded to
606 * nbconfig:0x60/0x64
607 */
608
609 set_nbmisc_enable_bits(nb_dev, 0x01, ~(1 << 8), (1 << 8));
610 }
611
612 /* enable CFG access to Dev8, which is the SB P2P Bridge */
613 static void enable_rs780_dev8(void)
614 {
615 set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
616 }
617
618 static void rs780_before_pci_init(void)
619 {
620 }
621
622 static void rs780_early_setup(void)
623 {
624 device_t nb_dev = PCI_DEV(0, 0, 0);
625 printk(BIOS_INFO, "rs780_early_setup()\n");
626
627 /* The printk(BIOS_INFO, s) below cause the system unstable. */
628 switch (get_nb_rev(nb_dev)) {
629 case REV_RS780_A11:
630 /* printk(BIOS_INFO, "NB Revision is A11.\n"); */
631 break;
632 case REV_RS780_A12:
633 /* printk(BIOS_INFO, "NB Revision is A12.\n"); */
634 break;
635 case REV_RS780_A13:
636 /* printk(BIOS_INFO, "NB Revision is A13.\n"); */
637 break;
638 }
639
640 if (is_famly10())
641 fam10_optimization();
642 else
643 k8_optimization();
644
645 rs780_por_init(nb_dev);
646 }
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