src/southbridge/amd/pi/hudson/sm.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <device/device.h>
  18 #include <device/pci.h>
  19 #include <device/pci_ids.h>
  20 #include <device/pci_ops.h>
  21 #include <device/smbus.h>
  22 #include <pc80/mc146818rtc.h>
  23 #include <arch/io.h>
  24 #include <cpu/x86/lapic.h>
  25 #include <arch/ioapic.h>
  26 #include <stdlib.h>
  27 #include "hudson.h"
  28 #include "smbus.c"
  29
  30 #define NMI_OFF 0
  31
  32 #define MAINBOARD_POWER_OFF 0
  33 #define MAINBOARD_POWER_ON 1
  34
  35 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
  36 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
  37 #endif
  38
  39 #define BIT0    (1 << 0)
  40 #define BIT1    (1 << 1)
  41 #define BIT2    (1 << 2)
  42 #define BIT3    (1 << 3)
  43 #define BIT4    (1 << 4)
  44 #define BIT5    (1 << 5)
  45 #define BIT6    (1 << 6)
  46 #define BIT7    (1 << 7)
  47
  48 #define BIT8    (1 << 8 )
  49 #define BIT9    (1 << 9 )
  50 #define BIT10   (1 << 10)
  51 #define BIT11   (1 << 11)
  52 #define BIT12   (1 << 12)
  53 #define BIT13   (1 << 13)
  54 #define BIT14   (1 << 14)
  55 #define BIT15   (1 << 15)
  56
  57 #define BIT16   (1 << 16)
  58 #define BIT17   (1 << 17)
  59 #define BIT18   (1 << 18)
  60 #define BIT19   (1 << 19)
  61 #define BIT20   (1 << 20)
  62 #define BIT21   (1 << 21)
  63 #define BIT22   (1 << 22)
  64 #define BIT23   (1 << 23)
  65 #define BIT24   (1 << 24)
  66 #define BIT25   (1 << 25)
  67 #define BIT26   (1 << 26)
  68 #define BIT27   (1 << 27)
  69 #define BIT28   (1 << 28)
  70 #define BIT29   (1 << 29)
  71 #define BIT30   (1 << 30)
  72 #define BIT31   (1 << 31)
  73
  74 /*
  75 * HUDSON enables all USB controllers by default in SMBUS Control.
  76 * HUDSON enables SATA by default in SMBUS Control.
  77 */
  78
  79 static void sm_init(device_t dev)
  80 {
  81         setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
  82 }
  83
  84 static int lsmbus_recv_byte(device_t dev)
  85 {
  86         u32 device;
  87         struct resource *res;
  88         struct bus *pbus;
  89
  90         device = dev->path.i2c.device;
  91         pbus = get_pbus_smbus(dev);
  92
  93         res = find_resource(pbus->dev, 0x90);
  94
  95         return do_smbus_recv_byte(res->base, device);
  96 }
  97
  98 static int lsmbus_send_byte(device_t dev, u8 val)
  99 {
 100         u32 device;
 101         struct resource *res;
 102         struct bus *pbus;
 103
 104         device = dev->path.i2c.device;
 105         pbus = get_pbus_smbus(dev);
 106
 107         res = find_resource(pbus->dev, 0x90);
 108
 109         return do_smbus_send_byte(res->base, device, val);
 110 }
 111
 112 static int lsmbus_read_byte(device_t dev, u8 address)
 113 {
 114         u32 device;
 115         struct resource *res;
 116         struct bus *pbus;
 117
 118         device = dev->path.i2c.device;
 119         pbus = get_pbus_smbus(dev);
 120
 121         res = find_resource(pbus->dev, 0x90);
 122
 123         return do_smbus_read_byte(res->base, device, address);
 124 }
 125
 126 static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
 127 {
 128         u32 device;
 129         struct resource *res;
 130         struct bus *pbus;
 131
 132         device = dev->path.i2c.device;
 133         pbus = get_pbus_smbus(dev);
 134
 135         res = find_resource(pbus->dev, 0x90);
 136
 137         return do_smbus_write_byte(res->base, device, address, val);
 138 }
 139 static struct smbus_bus_operations lops_smbus_bus = {
 140         .recv_byte = lsmbus_recv_byte,
 141         .send_byte = lsmbus_send_byte,
 142         .read_byte = lsmbus_read_byte,
 143         .write_byte = lsmbus_write_byte,
 144 };
 145
 146 static void hudson_sm_read_resources(device_t dev)
 147 {
 148 }
 149
 150 static void hudson_sm_set_resources(struct device *dev)
 151 {
 152 }
 153
 154 static struct pci_operations lops_pci = {
 155         .set_subsystem = pci_dev_set_subsystem,
 156 };
 157 static struct device_operations smbus_ops = {
 158         .read_resources = hudson_sm_read_resources,
 159         .set_resources = hudson_sm_set_resources,
 160         .enable_resources = pci_dev_enable_resources,
 161         .init = sm_init,
 162         .scan_bus = scan_smbus,
 163         .ops_pci = &lops_pci,
 164         .ops_smbus_bus = &lops_smbus_bus,
 165 };
 166 static const struct pci_driver smbus_driver __pci_driver = {
 167         .ops = &smbus_ops,
 168         .vendor = PCI_VENDOR_ID_AMD,
 169         .device = PCI_DEVICE_ID_ATI_SB900_SM,
 170 };