src/southbridge/amd/cs5535/cs5535.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Nils Jacobs
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef _CS5535_H
  18 #define _CS5535_H
  19
  20 /*      SouthBridge Equates */
  21 #define CS5535_GLINK_PORT_NUM   0x02    /* port of the SouthBridge */
  22 #define NB_PCI                  ((2     << 29) + (4 << 26))     /* NB GLPCI is in the same location on all Geodes. */
  23 #define MSR_SB                  ((CS5535_GLINK_PORT_NUM << 23) + NB_PCI)        /* address to the SouthBridge */
  24 #define SB_SHIFT                20      /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
  25
  26 #define CS5535_DEV_NUM          0x0F    /* default PCI device number for CS5535 */
  27 #define SMBUS_IO_BASE           0x6000
  28 #define GPIO_IO_BASE            0x6100
  29 #define MFGPT_IO_BASE           0x6200
  30 #define ACPI_IO_BASE            0x9C00
  31 #define PMS_IO_BASE             0x9D00
  32
  33 /* Cs5536 as follows. */
  34 /*      SB_GLIU */
  35 /*      port0 - GLIU */
  36 /*      port1 - GLPCI */
  37 /*      port2 - USB Controller #2 */
  38 /*      port3 - ATA-5 Controller */
  39 /*      port4 - MDD */
  40 /*      port5 - AC97 */
  41 /*      port6 - USB Controller #1 */
  42 /*      port7 - GLCP */
  43
  44 #define MSR_SB_GLIU             ((9 << 14) + MSR_SB)            /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
  45 #define MSR_SB_GLPCI            (MSR_SB)                        /* 5100xxxx - don't go to the GLIU */
  46 #define MSR_SB_USB2             ((2 << SB_SHIFT) + MSR_SB)      /* 5120xxxx */
  47 #define MSR_SB_ATA              ((3 << SB_SHIFT) + MSR_SB)      /* 5130xxxx */
  48 #define MSR_SB_MDD              ((4 << SB_SHIFT) + MSR_SB)      /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
  49 #define MSR_SB_AC97             ((5 << SB_SHIFT) + MSR_SB)      /* 5150xxxx */
  50 #define MSR_SB_USB1             ((6 << SB_SHIFT) + MSR_SB)      /* 5160xxxx */
  51 #define MSR_SB_GLCP             ((7 << SB_SHIFT) + MSR_SB)      /* 5170xxxx */
  52
  53 /* GLIU */
  54 #define GLIU_SB_GLD_MSR_PM      (MSR_SB_GLIU + 0x04)
  55
  56 /* USB1 */
  57 #define USB1_SB_GLD_MSR_CONF    (MSR_SB_USB1 + 0x01)
  58 #define USB1_SB_GLD_MSR_PM      (MSR_SB_USB1 + 0x04)
  59
  60 /* USB2 */
  61 #define USB2_SB_GLD_MSR_CONF    (MSR_SB_USB2 + 0x01)
  62 #define USB2_SB_GLD_MSR_PM      (MSR_SB_USB2 + 0x04)
  63
  64 /* ATA */
  65 #define ATA_SB_GLD_MSR_CONF     (MSR_SB_ATA + 0x01)
  66 #define ATA_SB_GLD_MSR_ERR      (MSR_SB_ATA + 0x03)
  67 #define ATA_SB_GLD_MSR_PM       (MSR_SB_ATA + 0x04)
  68 #define ATA_SB_IDE_CFG          (MSR_SB_ATA + 0x10)
  69
  70 /* AC97 */
  71 #define AC97_SB_GLD_MSR_CONF    (MSR_SB_AC97 + 0x01)
  72 #define AC97_SB_GLD_MSR_PM      (MSR_SB_AC97 + 0x04)
  73
  74 /* GLPCI */
  75 #define GLPCI_SB_GLD_MSR_PM     (MSR_SB_GLPCI + 0x04)
  76 #define GLPCI_SB_CTRL           (MSR_SB_GLPCI + 0x10)
  77 #define GLPCI_CRTL_PPIDE_SET    (1 << 17)
  78
  79 /* GLCP */
  80 #define GLCP_SB_GLD_MSR_PM      (MSR_SB_GLCP + 0x04)
  81
  82 /* MDD */
  83 #define MDD_SB_GLD_MSR_CONF     (MSR_SB_MDD + 0x01)
  84 #define MDD_SB_GLD_MSR_PM       (MSR_SB_MDD + 0x04)
  85 #define MDD_LBAR_SMB            (MSR_SB_MDD + 0x0B)
  86 #define MDD_LBAR_GPIO           (MSR_SB_MDD + 0x0C)
  87 #define MDD_LBAR_MFGPT          (MSR_SB_MDD + 0x0D)
  88 #define MDD_LBAR_ACPI           (MSR_SB_MDD + 0x0E)
  89 #define MDD_LBAR_PMS            (MSR_SB_MDD + 0x0F)
  90 #define MDD_LBAR_FLSH0          (MSR_SB_MDD + 0x10)
  91 #define MDD_LBAR_FLSH1          (MSR_SB_MDD + 0x11)
  92 #define MDD_LBAR_FLSH2          (MSR_SB_MDD + 0x12)
  93 #define MDD_LBAR_FLSH3          (MSR_SB_MDD + 0x13)
  94 #define MDD_PIN_OPT             (MSR_SB_MDD + 0x15)
  95 #define MDD_NORF_CNTRL          (MSR_SB_MDD + 0x18)
  96
  97 /* GPIO */
  98 #define GPIOL_2_SET             (1 << 2)
  99
 100 /* GPIO LOW Bank Bit Registers */
 101 #define GPIOL_INPUT_ENABLE      (0x20)
 102 #define GPIOL_IN_AUX1_SELECT    (0x34)
 103
 104 /* FLASH device macros */
 105 #define FLASH_TYPE_NONE         0       /* No flash device installed */
 106 #define FLASH_TYPE_NAND         1       /* NAND device */
 107
 108 #define FLASH_IF_MEM            1       /* Memory or memory-mapped I/O interface for Flash device */
 109
 110 /* Flash Memory Mask values */
 111 #define FLASH_MEM_4K            0xFFFFF000
 112
 113 #if !defined(__ASSEMBLER__)
 114 #if defined(__PRE_RAM__)
 115 void cs5535_disable_internal_uart(void);
 116 #else
 117 void chipsetinit(void);
 118 #endif
 119 #endif
 120
 121 #endif                          /* _CS5535_H */