src/southbridge/amd/cimx/sb800/late.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2014 Sage Electronic Engineering, LLC.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17
  18 #include <device/device.h>      /* device_t */
  19 #include <device/pci.h>         /* device_operations */
  20 #include <device/pci_ids.h>
  21 #include <bootstate.h>
  22 #include <arch/ioapic.h>
  23 #include <device/smbus.h>       /* smbus_bus_operations */
  24 #include <pc80/mc146818rtc.h>
  25 #include <pc80/i8254.h>
  26 #include <pc80/i8259.h>
  27 #include <console/console.h>    /* printk */
  28 #include <arch/acpi.h>
  29 #include <device/pci_ehci.h>
  30 #include "lpc.h"                /* lpc_read_resources */
  31 #include "SBPLATFORM.h"         /* Platform Specific Definitions */
  32 #include "cfg.h"                /* sb800 Cimx configuration */
  33 #include "chip.h"               /* struct southbridge_amd_cimx_sb800_config */
  34 #include "sb_cimx.h"            /* AMD CIMX wrapper entries */
  35 #include "smbus.h"
  36 #include "fan.h"
  37 #include <southbridge/amd/common/amd_pci_util.h>
  38
  39 /*implement in mainboard.c*/
  40 void set_pcie_reset(void);
  41 void set_pcie_dereset(void);
  42
  43
  44 static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
  45 static AMDSBCFG *sb_config = &sb_late_cfg;
  46
  47
  48 /**
  49  * @brief Entry point of Southbridge CIMx callout
  50  *
  51  * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
  52  *
  53  * @param[in] func      Southbridge CIMx Function ID.
  54  * @param[in] data      Southbridge Input Data.
  55  * @param[in] config    Southbridge configuration structure pointer.
  56  *
  57  */
  58 static u32 sb800_callout_entry(u32 func, u32 data, void* config)
  59 {
  60         u32 ret = 0;
  61         printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
  62         switch (func) {
  63         case CB_SBGPP_RESET_ASSERT:
  64                 set_pcie_reset();
  65                 break;
  66
  67         case CB_SBGPP_RESET_DEASSERT:
  68                 set_pcie_dereset();
  69                 break;
  70
  71         case IMC_FIRMWARE_FAIL:
  72                 break;
  73
  74         default:
  75                 break;
  76         }
  77
  78         printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__);
  79         return ret;
  80 }
  81
  82 #define HOST_CAP                  0x00 /* host capabilities */
  83 #define HOST_CTL                  0x04 /* global host control */
  84 #define HOST_IRQ_STAT             0x08 /* interrupt status */
  85 #define HOST_PORTS_IMPL           0x0c /* bitmap of implemented ports */
  86
  87 #define HOST_CTL_AHCI_EN          (1 << 31) /* AHCI enabled */
  88 static void ahci_raid_init(struct device *dev)
  89 {
  90         u8 irq = 0;
  91         void *bar5;
  92         u32 caps, ports, val;
  93
  94         val = pci_read_config16(dev, PCI_CLASS_DEVICE);
  95         if (val == PCI_CLASS_STORAGE_SATA) {
  96                 printk(BIOS_DEBUG, "AHCI controller ");
  97         } else if (val == PCI_CLASS_STORAGE_RAID) {
  98                 printk(BIOS_DEBUG, "RAID controller ");
  99         } else {
 100                 printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val);
 101                 return;
 102         }
 103
 104         irq = pci_read_config8(dev, PCI_INTERRUPT_LINE);
 105         bar5 = (void *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
 106         printk(BIOS_DEBUG, "IOMEM base: %p, IRQ: 0x%X\n", bar5, irq);
 107
 108         caps = read32(bar5 + HOST_CAP);
 109         caps = (caps & 0x1F) + 1;
 110         ports= read32(bar5 + HOST_PORTS_IMPL);
 111         printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports);
 112
 113         /* make sure ahci is enabled */
 114         val = read32(bar5 + HOST_CTL);
 115         if (!(val & HOST_CTL_AHCI_EN)) {
 116                 write32(bar5 + HOST_CTL, val | HOST_CTL_AHCI_EN);
 117         }
 118
 119         dev->command |= PCI_COMMAND_MASTER;
 120         pci_write_config8(dev, PCI_COMMAND, dev->command);
 121         printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n");
 122 }
 123
 124 static struct pci_operations lops_pci = {
 125         .set_subsystem = pci_dev_set_subsystem,
 126 };
 127
 128 static void lpc_init(device_t dev)
 129 {
 130         printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
 131
 132         cmos_check_update_date();
 133
 134         /* Initialize the real time clock.
 135          * The 0 argument tells cmos_init not to
 136          * update CMOS unless it is invalid.
 137          * 1 tells cmos_init to always initialize the CMOS.
 138          */
 139         cmos_init(0);
 140
 141         setup_i8259(); /* Initialize i8259 pic */
 142         setup_i8254(); /* Initialize i8254 timers */
 143
 144         printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n");
 145 }
 146
 147 unsigned long acpi_fill_mcfg(unsigned long current)
 148 {
 149         /* Just a dummy */
 150         return current;
 151 }
 152
 153 static struct device_operations lpc_ops = {
 154         .read_resources = lpc_read_resources,
 155         .set_resources = lpc_set_resources,
 156         .enable_resources = pci_dev_enable_resources,
 157 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 158         .write_acpi_tables = acpi_write_hpet,
 159 #endif
 160         .init = lpc_init,
 161         .scan_bus = scan_lpc_bus,
 162         .ops_pci = &lops_pci,
 163 };
 164
 165 static const struct pci_driver lpc_driver __pci_driver = {
 166         .ops = &lpc_ops,
 167         .vendor = PCI_VENDOR_ID_ATI,
 168         .device = PCI_DEVICE_ID_ATI_SB800_LPC,
 169 };
 170
 171 static struct device_operations sata_ops = {
 172         .read_resources = pci_dev_read_resources,
 173         .set_resources = pci_dev_set_resources,
 174         .enable_resources = pci_dev_enable_resources,
 175         .init = ahci_raid_init,
 176         .scan_bus = 0,
 177         .ops_pci = &lops_pci,
 178 };
 179
 180 static const struct pci_driver ahci_driver __pci_driver = {
 181         .ops = &sata_ops,
 182         .vendor = PCI_VENDOR_ID_ATI,
 183         .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI,
 184 };
 185
 186 static const struct pci_driver raid_driver __pci_driver = {
 187         .ops = &sata_ops,
 188         .vendor = PCI_VENDOR_ID_ATI,
 189         .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID,
 190 };
 191 static const struct pci_driver raid5_driver __pci_driver = {
 192         .ops = &sata_ops,
 193         .vendor = PCI_VENDOR_ID_ATI,
 194         .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5,
 195 };
 196
 197 static struct device_operations usb_ops = {
 198         .read_resources = pci_ehci_read_resources,
 199         .set_resources = pci_dev_set_resources,
 200         .enable_resources = pci_dev_enable_resources,
 201         .init = 0,
 202         .scan_bus = 0,
 203         .ops_pci = &lops_pci,
 204 };
 205
 206 /*
 207  * The pci id of usb ctrl 0 and 1 are the same.
 208  */
 209 static const struct pci_driver usb_ohci123_driver __pci_driver = {
 210         .ops = &usb_ops,
 211         .vendor = PCI_VENDOR_ID_ATI,
 212         .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
 213 };
 214
 215 static const struct pci_driver usb_ehci123_driver __pci_driver = {
 216         .ops = &usb_ops,
 217         .vendor = PCI_VENDOR_ID_ATI,
 218         .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
 219 };
 220
 221 static const struct pci_driver usb_ohci4_driver __pci_driver = {
 222         .ops = &usb_ops,
 223         .vendor = PCI_VENDOR_ID_ATI,
 224         .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
 225 };
 226
 227
 228 static struct device_operations azalia_ops = {
 229         .read_resources = pci_dev_read_resources,
 230         .set_resources = pci_dev_set_resources,
 231         .enable_resources = pci_dev_enable_resources,
 232         .init = 0,
 233         .scan_bus = 0,
 234         .ops_pci = &lops_pci,
 235 };
 236
 237 static const struct pci_driver azalia_driver __pci_driver = {
 238         .ops = &azalia_ops,
 239         .vendor = PCI_VENDOR_ID_ATI,
 240         .device = PCI_DEVICE_ID_ATI_SB800_HDA,
 241 };
 242
 243
 244 static struct device_operations gec_ops = {
 245         .read_resources = pci_dev_read_resources,
 246         .set_resources = pci_dev_set_resources,
 247         .enable_resources = pci_dev_enable_resources,
 248         .init = 0,
 249         .scan_bus = 0,
 250         .ops_pci = &lops_pci,
 251 };
 252
 253 static const struct pci_driver gec_driver __pci_driver = {
 254         .ops = &gec_ops,
 255         .vendor = PCI_VENDOR_ID_ATI,
 256         .device = PCI_DEVICE_ID_ATI_SB800_GEC,
 257 };
 258
 259 /**
 260  *  Fill build time defaults.
 261  */
 262 static void sb800_init(void *chip_info)
 263 {
 264         sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
 265         sb800_cimx_config(sb_config);
 266
 267         /* Initially enable all GPP ports 0 to 3 */
 268         abcfg_reg(0xc0, 0x01FF, 0x0F4);
 269 }
 270
 271 /**
 272  * South Bridge CIMx ramstage entry point wrapper.
 273  */
 274 void sb_Before_Pci_Init(void)
 275 {
 276         sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
 277         AmdSbDispatcher(sb_config);
 278 }
 279
 280 void sb_After_Pci_Init(void)
 281 {
 282         sb_config->StdHeader.Func = SB_AFTER_PCI_INIT;
 283         AmdSbDispatcher(sb_config);
 284 }
 285
 286 void sb_Mid_Post_Init(void)
 287 {
 288         sb_config->StdHeader.Func = SB_MID_POST_INIT;
 289         AmdSbDispatcher(sb_config);
 290 }
 291
 292 void sb_Late_Post(void)
 293 {
 294         sb_config->StdHeader.Func = SB_LATE_POST_INIT;
 295         AmdSbDispatcher(sb_config);
 296 }
 297
 298 void sb_Before_Pci_Restore_Init(void)
 299 {
 300         sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT;
 301         AmdSbDispatcher(sb_config);
 302 }
 303
 304 void sb_After_Pci_Restore_Init(void)
 305 {
 306         sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT;
 307         AmdSbDispatcher(sb_config);
 308 }
 309
 310 /*
 311  * Update the PCI devices with a valid IRQ number
 312  * that is set in the mainboard PCI_IRQ structures.
 313  */
 314 static void set_pci_irqs(void *unused)
 315 {
 316         /* Write PCI_INTR regs 0xC00/0xC01 */
 317         write_pci_int_table();
 318
 319         /* Write IRQs for all devicetree enabled devices */
 320         write_pci_cfg_irqs();
 321 }
 322
 323 /*
 324  * Hook this function into the PCI state machine
 325  * on entry into BS_DEV_ENABLE.
 326  */
 327 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
 328
 329 /**
 330  * @brief SB Cimx entry point sbBeforePciInit wrapper
 331  */
 332 static void sb800_enable(device_t dev)
 333 {
 334         struct southbridge_amd_cimx_sb800_config *sb_chip =
 335                 (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
 336
 337         switch (dev->path.pci.devfn) {
 338         case (0x11 << 3) | 0: /* 0:11.0  SATA */
 339                 if (dev->enabled) {
 340                         sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
 341                         if (1 == sb_chip->boot_switch_sata_ide)
 342                                 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
 343                         else if (0 == sb_chip->boot_switch_sata_ide)
 344                                 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
 345                 } else {
 346                         sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
 347                 }
 348                 break;
 349
 350         case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
 351                 clear_ioapic(VIO_APIC_VADDR);
 352 #if CONFIG_CPU_AMD_AGESA
 353                 /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
 354                 setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
 355 #else
 356                 /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
 357 #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
 358                 /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
 359                 setup_ioapic(VIO_APIC_VADDR,
 360                              CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
 361 #elif (CONFIG_APIC_ID_OFFSET > 0)
 362                 /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
 363                 setup_ioapic(VIO_APIC_VADDR, 0);
 364 #else
 365 #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
 366 #endif
 367 #endif
 368                 break;
 369
 370         case (0x14 << 3) | 1: /* 0:14:1 IDE */
 371                 break;
 372
 373         case (0x14 << 3) | 2: /* 0:14:2 HDA */
 374                 if (dev->enabled) {
 375                         if (AZALIA_DISABLE == sb_config->AzaliaController) {
 376                                 sb_config->AzaliaController = AZALIA_AUTO;
 377                         }
 378                 } else {
 379                         sb_config->AzaliaController = AZALIA_DISABLE;
 380                 }
 381                 break;
 382
 383
 384         case (0x14 << 3) | 3: /* 0:14:3 LPC */
 385                 /* Initialize the fans */
 386 #if CONFIG_SB800_IMC_FAN_CONTROL
 387                 init_sb800_IMC_fans(dev);
 388 #elif CONFIG_SB800_MANUAL_FAN_CONTROL
 389                 init_sb800_MANUAL_fans(dev);
 390 #endif
 391                 break;
 392
 393         case (0x14 << 3) | 4: /* 0:14:4 PCI */
 394                 /* PcibConfig [PM_Reg: EAh], PCIDisable [Bit0]
 395                  * 'PCIDisable' set to 0 to enable P2P bridge.
 396                  * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
 397                  *              to function as GPIO {GPIO 35:0}.
 398                  */
 399                 if (!sb_chip->disconnect_pcib && dev->enabled)
 400                         RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
 401                 else
 402                         RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0);
 403                 break;
 404
 405         case (0x14 << 3) | 6: /* 0:14:6 GEC */
 406                 if (dev->enabled) {
 407                         sb_config->GecConfig = 0;
 408                 } else {
 409                         sb_config->GecConfig = 1;
 410                 }
 411                 break;
 412
 413         case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
 414                 {
 415                         device_t device;
 416                         for (device = dev; device; device = device->next) {
 417                                 if (dev->path.type != DEVICE_PATH_PCI) continue;
 418                                 if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
 419                                 sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
 420                         }
 421
 422                         /*
 423                          * GPP_CFGMODE_X4000: PortA Lanes[3:0]
 424                          * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
 425                          * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
 426                          * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
 427                          */
 428                         sb_config->GppLinkConfig = sb_chip->gpp_configuration;
 429                 }
 430                 break;
 431
 432         case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
 433                 sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
 434                 break;
 435         case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
 436                 sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled;
 437                 break;
 438         case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
 439                 sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled;
 440                 break;
 441         case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
 442                 sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled;
 443                 break;
 444         case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
 445                 sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled;
 446                 break;
 447         case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
 448                 sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled;
 449                 break;
 450         case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
 451                 sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
 452
 453                 /* call the CIMX entry at the last sb800 device,
 454                  * so make sure the mainboard devicetree is complete
 455                  */
 456                 if (!acpi_is_wakeup_s3())
 457                         sb_Before_Pci_Init();
 458                 else
 459                         sb_Before_Pci_Restore_Init();
 460                 break;
 461
 462         default:
 463                 break;
 464         }
 465 }
 466
 467 struct chip_operations southbridge_amd_cimx_sb800_ops = {
 468         CHIP_NAME("ATI SB800")
 469         .init = sb800_init,
 470         .enable_dev = sb800_enable,
 471 };