tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / southbridge / amd / cimx / sb800 / SBPLATFORM.h
blobc93320717984d9d240e28be55fe2b1a0463fb7f1
1 /*
2 *****************************************************************************
4 * This file is part of the coreboot project.
6 * Copyright (C) 2011 Advanced Micro Devices, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 * ***************************************************************************
20 #ifndef _AMD_SBPLATFORM_H_
21 #define _AMD_SBPLATFORM_H_
23 #include <stddef.h>
25 typedef unsigned long long PLACEHOLDER;
27 #ifndef SBOEM_ACPI_RESTORE_SWSMI
28 #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
29 #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
30 #endif
32 #ifndef _AMD_NB_CIM_X_PROTOCOL_H_
35 /// Extended PCI Address
36 typedef struct _EXT_PCI_ADDR {
37 UINT32 Reg :16; ///< / PCI Register
38 UINT32 Func:3; ///< / PCI Function
39 UINT32 Dev :5; ///< / PCI Device
40 UINT32 Bus :8; ///< / PCI Address
41 } EXT_PCI_ADDR;
43 /// PCI Address
44 typedef union _PCI_ADDR {
45 UINT32 ADDR; ///< / 32 bit Address
46 EXT_PCI_ADDR Addr; ///< / Extended PCI Address
47 } PCI_ADDR;
49 #endif
50 #define FIXUP_PTR(ptr) ptr
52 #if CONFIG_SB800_IMC_FWM
53 #define IMC_ENABLE_OVER_WRITE 0x01
54 #endif
56 #include <console/console.h>
57 #include "AmdSbLib.h"
58 #include "Amd.h"
59 #include "SB800.h"
60 #include "SBTYPE.h"
61 #include "ACPILIB.h"
62 #include "SBDEF.h"
63 #include "AMDSBLIB.h"
64 #include "SBSUBFUN.h"
65 #include "platform_cfg.h" /* mainboard specific configuration */
66 #include "OEM.h" /* platform default configuration */
67 #include "AMD.h"
70 //------------------------------------------------------------------------------------------------------------------------//
71 /**
72 * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over
73 * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
74 * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
75 * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
76 * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
77 * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
78 * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
79 * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
80 * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
81 * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
82 * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
83 * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
84 * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
85 * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
86 * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
87 * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
88 * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
89 * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
90 * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11)
91 * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
92 * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
93 * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
94 * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
95 * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
96 * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
97 * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
98 * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
99 * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
100 * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
101 * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
102 * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
103 * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
104 * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
105 * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
106 * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
107 * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
109 #define SB_CIMx_PARAMETER 0x02
111 // Generic
112 #define cimSpreadSpectrumDefault TRUE
113 #define cimSpreadSpectrumTypeDefault 0x00 // Normal
114 #define cimHpetTimerDefault TRUE
115 #define cimHpetMsiDisDefault FALSE // Enable
116 #define cimIrConfigDefault 0x00 // Disable
117 #define cimSpiFastReadEnableDefault 0x01 // Enable
118 #define cimSpiFastReadSpeedDefault 0x01 // 33 MHz
119 #define cimSioHwmPortEnableDefault FALSE
120 // GPP/AB Controller
121 #define cimNbSbGen2Default TRUE
122 #define cimAlinkPhyPllPowerDownDefault TRUE
123 #define cimResetCpuOnSyncFloodDefault TRUE
124 #define cimGppGen2Default FALSE
125 #define cimGppMemWrImproveDefault TRUE
126 #define cimGppPortAspmDefault FALSE
127 #define cimGppLaneReversalDefault FALSE
128 #define cimGppPhyPllPowerDownDefault TRUE
129 // USB Controller
130 #define cimUsbPhyPowerDownDefault FALSE
131 // GEC Controller
132 #define cimSBGecDebugBusDefault FALSE
133 #define cimSBGecPwrDefault 0x03
134 // Sata Controller
135 #define cimSataSetMaxGen2Default 0x00
136 #define cimSATARefClkSelDefault 0x10
137 #define cimSATARefDivSelDefault 0x80
138 #define cimSataAggrLinkPmCapDefault TRUE
139 #define cimSataPortMultCapDefault TRUE
140 #define cimSataPscCapDefault 0x00 // Enable
141 #define cimSataSscCapDefault 0x00 // Enable
142 #define cimSataFisBasedSwitchingDefault FALSE
143 #define cimSataCccSupportDefault FALSE
144 #define cimSataClkAutoOffDefault FALSE
145 #define cimNativepciesupportDefault FALSE
146 // Fusion Related
147 #define cimAcDcMsgDefault FALSE
148 #define cimTimerTickTrackDefault FALSE
149 #define cimClockInterruptTagDefault FALSE
150 #define cimOhciTrafficHandingDefault FALSE
151 #define cimEhciTrafficHandingDefault FALSE
152 #define cimFusionMsgCMultiCoreDefault FALSE
153 #define cimFusionMsgCStageDefault FALSE
155 #include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
157 #if CONFIG_HAVE_ACPI_RESUME
158 #include <spi-generic.h>
159 #endif
161 #define BIOSRAM_INDEX 0xcd4
162 #define BIOSRAM_DATA 0xcd5
164 #endif // _AMD_SBPLATFORM_H_