2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 // Use simple device model for this file even in ramstage
17 #define __SIMPLE_DEVICE__
22 #define HT_INIT_CONTROL 0x6C
23 #define HTIC_BIOSR_Detect (1<<5)
25 #define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
27 static inline void set_bios_reset(void)
34 nodes
= ((pci_read_config32(PCI_DEV(CONFIG_CBB
, CONFIG_CDB
, 0), 0x60) >> 4) & 7) + 1;
35 for(i
= 0; i
< nodes
; i
++) {
37 htic
= pci_read_config32(dev
, HT_INIT_CONTROL
);
38 htic
&= ~HTIC_BIOSR_Detect
;
39 pci_write_config32(dev
, HT_INIT_CONTROL
, htic
);
46 /* Try rebooting through port 0xcf9 */
47 /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
48 outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
49 outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);