src/southbridge/amd/cimx/sb700/bootblock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16
  17 #include <arch/io.h>
  18
  19 static void sb700_enable_rom(void)
  20 {
  21         u32 word;
  22         u32 dword;
  23         pci_devfn_t dev;
  24
  25         dev = PCI_DEV(0, 0x14, 0x03);
  26         /* SB700 LPC Bridge 0:20:3:44h.
  27          * BIT6: Port Enable for serial port 0x3f8-0x3ff
  28          * BIT29: Port Enable for KBC port 0x60 and 0x64
  29          * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
  30          */
  31         dword = pci_io_read_config32(dev, 0x44);
  32         //dword |= (1<<6) | (1<<29) | (1<<30) ;
  33         /*Turn on all of LPC IO Port decode enable */
  34         dword = 0xffffffff;
  35         pci_io_write_config32(dev, 0x44, dword);
  36
  37         /* SB700 LPC Bridge 0:20:3:48h.
  38          * BIT0: Port Enable for SuperIO 0x2E-0x2F
  39          * BIT1: Port Enable for SuperIO 0x4E-0x4F
  40          * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
  41          * BIT6: Port Enable for RTC IO 0x70-0x73
  42          * BIT21: Port Enable for Port 0x80
  43          */
  44         dword = pci_io_read_config32(dev, 0x48);
  45         dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
  46         pci_io_write_config32(dev, 0x48, dword);
  47
  48         /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
  49         /* Set the 4MB enable bits */
  50         word = pci_io_read_config16(dev, 0x6c);
  51         word = 0xFFC0;
  52         pci_io_write_config16(dev, 0x6c, word);
  53 }
  54
  55 static void bootblock_southbridge_init(void)
  56 {
  57         /* Setup the rom access for 2M */
  58         sb700_enable_rom();
  59 }