src/southbridge/amd/agesa/hudson/sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <device/device.h>
  18 #include <delay.h>
  19 #include <device/pci.h>
  20 #include <device/pci_ids.h>
  21 #include <device/pci_ops.h>
  22 #include <arch/io.h>
  23 #include "hudson.h"
  24
  25
  26 static void sata_init(struct device *dev)
  27 {
  28 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
  29         /**************************************
  30          * Configure the SATA port multiplier *
  31          **************************************/
  32         #define BYTE_TO_DWORD_OFFSET(x) (x/4)
  33         #define AHCI_BASE_ADDRESS_REG 0x24
  34         #define MISC_CONTROL_REG 0x40
  35         #define UNLOCK_BIT (1<<0)
  36         #define SATA_CAPABILITIES_REG 0xFC
  37         #define CFG_CAP_SPM (1<<12)
  38
  39         volatile u32 *ahci_ptr =
  40                 (u32*)(uintptr_t)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00);
  41         u32 temp;
  42
  43         /* unlock the write-protect */
  44         temp = pci_read_config32(dev, MISC_CONTROL_REG);
  45         temp |= UNLOCK_BIT;
  46         pci_write_config32(dev, MISC_CONTROL_REG, temp);
  47
  48         /* set the SATA AHCI mode to allow port expanders */
  49         *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM;
  50
  51         /* lock the write-protect */
  52         temp = pci_read_config32(dev, MISC_CONTROL_REG);
  53         temp &= ~UNLOCK_BIT;
  54         pci_write_config32(dev, MISC_CONTROL_REG, temp);
  55 #endif
  56 };
  57
  58 static struct pci_operations lops_pci = {
  59         /* .set_subsystem = pci_dev_set_subsystem, */
  60 };
  61
  62 static struct device_operations sata_ops = {
  63         .read_resources = pci_dev_read_resources,
  64         .set_resources = pci_dev_set_resources,
  65         .enable_resources = pci_dev_enable_resources,
  66         .init = sata_init,
  67         .scan_bus = 0,
  68         .ops_pci = &lops_pci,
  69 };
  70
  71 static const struct pci_driver sata0_driver __pci_driver = {
  72         .ops = &sata_ops,
  73         .vendor = PCI_VENDOR_ID_AMD,
  74         .device = PCI_DEVICE_ID_ATI_SB900_SATA,
  75 };
  76
  77 static const struct pci_driver sata0_driver_ahci __pci_driver = {
  78         .ops = &sata_ops,
  79         .vendor = PCI_VENDOR_ID_AMD,
  80         .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI,
  81 };