src/southbridge/amd/agesa/hudson/acpi/lpc.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Sage Electronic Engineering, LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /* 0:14.3 - LPC */
  17 Device(LIBR) {
  18         Name(_ADR, 0x00140003)
  19         /* Method(_INI) {
  20         *       DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
  21         } */ /* End Method(_SB.SBRDG._INI) */
  22
  23         OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
  24         Field(CFG,DWordAcc,NoLock,Preserve){
  25                 Offset(0xA0),
  26                 BAR,32}         // SPI Controller Base Address Register (Index 0xA0)
  27
  28         Device(LDRC)    // LPC device: Resource consumption
  29         {
  30                 Name (_HID, EISAID("PNP0C02"))  // ID for Motherboard resources
  31                 Name (CRS, ResourceTemplate ()  // Current Motherboard resources
  32                 {
  33                         Memory32Fixed(ReadWrite,        // Setup for fixed resource location for SPI base address
  34                         0x00000000,                                     // Address Base
  35                         0x00000000,                                     // Address Length
  36                         BAR0                                            // Descriptor Name
  37                         )
  38                 })
  39
  40                 Method(_CRS,0,NotSerialized)
  41                 {
  42                         CreateDwordField(^CRS,^BAR0._BAS,SPIB)  // Field to hold SPI base address
  43                         CreateDwordField(^CRS,^BAR0._LEN,SPIL)  // Field to hold SPI address length
  44                         Store(BAR,SPIB)         // SPI base address mapped
  45                         Store(0x1000,SPIL)      // 4k space mapped
  46                         Return(CRS)
  47                 }
  48         }
  49
  50         /* Real Time Clock Device */
  51         Device(RTC0) {
  52                 Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
  53                 Name(_CRS, ResourceTemplate() {
  54                         IRQNoFlags(){8}
  55                         IO(Decode16,0x0070, 0x0070, 0, 2)
  56                 })
  57         } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
  58
  59         Device(TMR) {   /* Timer */
  60                 Name(_HID,EISAID("PNP0100"))    /* System Timer */
  61                 Name(_CRS, ResourceTemplate() {
  62                         IRQNoFlags(){0}
  63                         IO(Decode16, 0x0040, 0x0040, 0, 4)
  64                 })
  65         } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
  66
  67         Device(SPKR) {  /* Speaker */
  68                 Name(_HID,EISAID("PNP0800"))    /* AT style speaker */
  69                 Name(_CRS, ResourceTemplate() {
  70                         IO(Decode16, 0x0061, 0x0061, 0, 1)
  71                 })
  72         } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
  73
  74         Device(PIC) {
  75                 Name(_HID,EISAID("PNP0000"))    /* AT Interrupt Controller */
  76                 Name(_CRS, ResourceTemplate() {
  77                         IRQNoFlags(){2}
  78                         IO(Decode16,0x0020, 0x0020, 0, 2)
  79                         IO(Decode16,0x00A0, 0x00A0, 0, 2)
  80                 })
  81         } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
  82
  83         Device(MAD) { /* 8257 DMA */
  84                 Name(_HID,EISAID("PNP0200"))    /* Hardware Device ID */
  85                 Name(_CRS, ResourceTemplate() {
  86                         DMA(Compatibility,BusMaster,Transfer8){4}
  87                         IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
  88                         IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
  89                         IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
  90                         IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
  91                         IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
  92                         IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
  93                 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
  94         } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
  95
  96         Device(COPR) {
  97                 Name(_HID,EISAID("PNP0C04"))    /* Math Coprocessor */
  98                 Name(_CRS, ResourceTemplate() {
  99                         IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
 100                         IRQNoFlags(){13}
 101                 })
 102         } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
 103         #include "acpi/superio.asl"
 104 } /* end LIBR */