src/soc/samsung/exynos5420/dp_lowlevel.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * Author: Donghwa Lee <dh09.lee@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include <console/console.h>
  19 #include <delay.h>
  20 #include <soc/dp.h>
  21 #include <soc/fimd.h>
  22 #include <soc/i2c.h>
  23 #include <soc/power.h>
  24 #include <soc/sysreg.h>
  25 #include <stdlib.h>
  26 #include <string.h>
  27 #include <timer.h>
  28
  29 /* FIXME: I think the DP controller shouldn't be hardcoded here... */
  30 static struct exynos_dp * const dp_regs = (void *)EXYNOS5_DP1_BASE;
  31
  32 /* for debugging, it's nice to get control on a per-file basis.
  33  * I had a bit of a discussion with myself (boring!) about
  34  * how to do this and for the moment this is the easiest way.
  35  * These debugging statements allowed me to find the final bugs.
  36  */
  37
  38 #if 0
  39 static inline void fwadl(unsigned long l,void *v) {
  40         writel(l, v);
  41         printk(BIOS_SPEW, "W %p %p\n", v, (void *)l);
  42 }
  43 #define lwrite32(a,b) fwadl((unsigned long)(a), (void *)(b))
  44
  45 static inline unsigned long fradl(void *v) {
  46         unsigned long l = readl(v);
  47         printk(BIOS_SPEW, "R %p %p\n", v, (void *)l);
  48         return l;
  49 }
  50
  51 #define lread32(a) fradl((void *)(a))
  52 #else
  53 #define lwrite32(a,b) write32((void *)(b), (unsigned long)(a))
  54 #define lread32(a) read32((void *)(a))
  55 #endif
  56
  57 static void exynos_dp_enable_video_input(u32 enable)
  58 {
  59         u32 reg;
  60
  61         reg = lread32(&dp_regs->video_ctl1);
  62         reg &= ~VIDEO_EN_MASK;
  63
  64         /* enable video input*/
  65         if (enable)
  66                 reg |= VIDEO_EN_MASK;
  67
  68         lwrite32(reg, &dp_regs->video_ctl1);
  69
  70         return;
  71 }
  72
  73 void exynos_dp_disable_video_bist(void)
  74 {
  75         u32 reg;
  76         reg = lread32(&dp_regs->video_ctl4);
  77         reg &= ~VIDEO_BIST_MASK;
  78         lwrite32(reg, &dp_regs->video_ctl4);
  79 }
  80
  81 void exynos_dp_enable_video_mute(unsigned int enable)
  82 {
  83         u32 reg;
  84
  85         reg = lread32(&dp_regs->video_ctl1);
  86         reg &= ~(VIDEO_MUTE_MASK);
  87         if (enable)
  88                 reg |= VIDEO_MUTE_MASK;
  89
  90         lwrite32(reg, &dp_regs->video_ctl1);
  91
  92         return;
  93 }
  94
  95
  96 static void exynos_dp_init_analog_param(void)
  97 {
  98         u32 reg;
  99
 100         /*
 101          * Set termination
 102          * Normal bandgap, Normal swing, Tx terminal resistor 61 ohm
 103          * 24M Phy clock, TX digital logic power is 100:1.0625V
 104          */
 105         reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
 106                 SWING_A_30PER_G_NORMAL;
 107         lwrite32(reg, &dp_regs->analog_ctl1);
 108
 109         reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 110         lwrite32(reg, &dp_regs->analog_ctl2);
 111
 112         /*
 113          * Set power source for internal clk driver to 1.0625v.
 114          * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
 115          * Set VCO range of PLL +- 0uA
 116          */
 117         reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
 118         lwrite32(reg, &dp_regs->analog_ctl3);
 119
 120         /*
 121          * Set AUX TX terminal resistor to 102 ohm
 122          * Set AUX channel amplitude control
 123         */
 124         reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
 125         lwrite32(reg, &dp_regs->pll_filter_ctl1);
 126
 127         /*
 128          * PLL loop filter bandwidth
 129          * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
 130          * PLL digital power select: 1.2500V
 131          */
 132         reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
 133
 134         lwrite32(reg, &dp_regs->amp_tuning_ctl);
 135
 136         /*
 137          * PLL loop filter bandwidth
 138          * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
 139          * PLL digital power select: 1.1250V
 140          */
 141         reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
 142         lwrite32(reg, &dp_regs->pll_ctl);
 143 }
 144
 145 static void exynos_dp_init_interrupt(void)
 146 {
 147         /* Set interrupt registers to initial states */
 148
 149         /*
 150          * Disable interrupt
 151          * INT pin assertion polarity. It must be configured
 152          * correctly according to ICU setting.
 153          * 1 = assert high, 0 = assert low
 154          */
 155         lwrite32(INT_POL, &dp_regs->int_ctl);
 156
 157         /* Clear pending registers */
 158         lwrite32(0xff, &dp_regs->common_int_sta1);
 159         lwrite32(0xff, &dp_regs->common_int_sta2);
 160         lwrite32(0xff, &dp_regs->common_int_sta3);
 161         lwrite32(0xff, &dp_regs->common_int_sta4);
 162         lwrite32(0xff, &dp_regs->int_sta);
 163
 164         /* 0:mask,1: unmask */
 165         lwrite32(0x00, &dp_regs->int_sta_mask1);
 166         lwrite32(0x00, &dp_regs->int_sta_mask2);
 167         lwrite32(0x00, &dp_regs->int_sta_mask3);
 168         lwrite32(0x00, &dp_regs->int_sta_mask4);
 169         lwrite32(0x00, &dp_regs->int_sta_mask);
 170 }
 171
 172 void exynos_dp_reset(void)
 173 {
 174         u32 reg_func_1;
 175
 176         /*dp tx sw reset*/
 177         lwrite32(RESET_DP_TX, &dp_regs->tx_sw_reset);
 178
 179         exynos_dp_enable_video_input(DP_DISABLE);
 180         exynos_dp_disable_video_bist();
 181         exynos_dp_enable_video_mute(DP_DISABLE);
 182
 183         /* software reset */
 184         reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 185                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 186                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 187
 188         lwrite32(reg_func_1, &dp_regs->func_en1);
 189         lwrite32(reg_func_1, &dp_regs->func_en2);
 190
 191         mdelay(1);
 192
 193         exynos_dp_init_analog_param();
 194         exynos_dp_init_interrupt();
 195
 196         return;
 197 }
 198
 199 void exynos_dp_enable_sw_func(unsigned int enable)
 200 {
 201         u32 reg;
 202
 203         reg = lread32(&dp_regs->func_en1);
 204         reg &= ~(SW_FUNC_EN_N);
 205
 206         if (!enable)
 207                 reg |= SW_FUNC_EN_N;
 208
 209         lwrite32(reg, &dp_regs->func_en1);
 210
 211         return;
 212 }
 213
 214 unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
 215 {
 216         u32 reg;
 217
 218         reg = lread32(&dp_regs->phy_pd);
 219         switch (block) {
 220         case AUX_BLOCK:
 221                 reg &= ~(AUX_PD);
 222                 if (enable)
 223                         reg |= AUX_PD;
 224                 break;
 225         case CH0_BLOCK:
 226                 reg &= ~(CH0_PD);
 227                 if (enable)
 228                         reg |= CH0_PD;
 229                 break;
 230         case CH1_BLOCK:
 231                 reg &= ~(CH1_PD);
 232                 if (enable)
 233                         reg |= CH1_PD;
 234                 break;
 235         case CH2_BLOCK:
 236                 reg &= ~(CH2_PD);
 237                 if (enable)
 238                         reg |= CH2_PD;
 239                 break;
 240         case CH3_BLOCK:
 241                 reg &= ~(CH3_PD);
 242                 if (enable)
 243                         reg |= CH3_PD;
 244                 break;
 245         case ANALOG_TOTAL:
 246                 reg &= ~PHY_PD;
 247                 if (enable)
 248                         reg |= PHY_PD;
 249                 break;
 250         case POWER_ALL:
 251                 reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
 252                         CH3_PD);
 253                 if (enable)
 254                         reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
 255                                 CH2_PD | CH3_PD);
 256                 break;
 257         default:
 258                 printk(BIOS_ERR, "DP undefined block number : %d\n",  block);
 259                 return -1;
 260         }
 261
 262         lwrite32(reg, &dp_regs->phy_pd);
 263
 264         return 0;
 265 }
 266
 267 unsigned int exynos_dp_get_pll_lock_status(void)
 268 {
 269         u32 reg;
 270
 271         reg = lread32(&dp_regs->debug_ctl);
 272
 273         if (reg & PLL_LOCK)
 274                 return PLL_LOCKED;
 275         else
 276                 return PLL_UNLOCKED;
 277 }
 278
 279 static void exynos_dp_set_pll_power(unsigned int enable)
 280 {
 281         u32 reg;
 282
 283         reg = lread32(&dp_regs->pll_ctl);
 284         reg &= ~(DP_PLL_PD);
 285
 286         if (!enable)
 287                 reg |= DP_PLL_PD;
 288
 289         lwrite32(reg, &dp_regs->pll_ctl);
 290 }
 291
 292 int exynos_dp_init_analog_func(void)
 293 {
 294         int ret = EXYNOS_DP_SUCCESS;
 295         unsigned int retry_cnt = 10;
 296         u32 reg;
 297
 298         /*Power On All Analog block */
 299         exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
 300
 301         reg = PLL_LOCK_CHG;
 302         lwrite32(reg, &dp_regs->common_int_sta1);
 303
 304         reg = lread32(&dp_regs->debug_ctl);
 305         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 306         lwrite32(reg, &dp_regs->debug_ctl);
 307
 308         /*Assert DP PLL Reset*/
 309         reg = lread32(&dp_regs->pll_ctl);
 310         reg |= DP_PLL_RESET;
 311         lwrite32(reg, &dp_regs->pll_ctl);
 312
 313         mdelay(1);
 314
 315         /*Deassert DP PLL Reset*/
 316         reg = lread32(&dp_regs->pll_ctl);
 317         reg &= ~(DP_PLL_RESET);
 318         lwrite32(reg, &dp_regs->pll_ctl);
 319
 320         exynos_dp_set_pll_power(DP_ENABLE);
 321
 322         while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
 323                 mdelay(1);
 324                 retry_cnt--;
 325                 if (retry_cnt == 0) {
 326                         printk(BIOS_ERR, "DP dp's pll lock failed : retry : %d\n",
 327                                         retry_cnt);
 328                         return -1;
 329                 }
 330         }
 331
 332         printk(BIOS_DEBUG, "dp's pll lock success(%d)\n", retry_cnt);
 333
 334         /* Enable Serdes FIFO function and Link symbol clock domain module */
 335         reg = lread32(&dp_regs->func_en2);
 336         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 337                 | AUX_FUNC_EN_N);
 338         lwrite32(reg, &dp_regs->func_en2);
 339
 340         return ret;
 341 }
 342
 343 void exynos_dp_init_hpd(void)
 344 {
 345         u32 reg;
 346
 347         /* Clear interrupts related to Hot Plug Detect */
 348         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 349         lwrite32(reg, &dp_regs->common_int_sta4);
 350
 351         reg = INT_HPD;
 352         lwrite32(reg, &dp_regs->int_sta);
 353
 354         reg = lread32(&dp_regs->sys_ctl3);
 355         reg &= ~(F_HPD | HPD_CTRL);
 356         lwrite32(reg, &dp_regs->sys_ctl3);
 357
 358         return;
 359 }
 360
 361 static inline void exynos_dp_reset_aux(void)
 362 {
 363         u32 reg;
 364
 365         /* Disable AUX channel module */
 366         reg = lread32(&dp_regs->func_en2);
 367         reg |= AUX_FUNC_EN_N;
 368         lwrite32(reg, &dp_regs->func_en2);
 369
 370         return;
 371 }
 372
 373 void exynos_dp_init_aux(void)
 374 {
 375         u32 reg;
 376
 377         /* Clear interrupts related to AUX channel */
 378         reg = RPLY_RECEIV | AUX_ERR;
 379         lwrite32(reg, &dp_regs->int_sta);
 380
 381         exynos_dp_reset_aux();
 382
 383         /* Disable AUX transaction H/W retry */
 384         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
 385                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 386         lwrite32(reg, &dp_regs->aux_hw_retry_ctl);
 387
 388         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 389         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 390         lwrite32(reg, &dp_regs->aux_ch_defer_ctl);
 391
 392         /* Enable AUX channel module */
 393         reg = lread32(&dp_regs->func_en2);
 394         reg &= ~AUX_FUNC_EN_N;
 395         lwrite32(reg, &dp_regs->func_en2);
 396
 397         return;
 398 }
 399
 400 void exynos_dp_config_interrupt(void)
 401 {
 402         u32 reg;
 403
 404         /* 0: mask, 1: unmask */
 405         reg = COMMON_INT_MASK_1;
 406         lwrite32(reg, &dp_regs->common_int_mask1);
 407
 408         reg = COMMON_INT_MASK_2;
 409         lwrite32(reg, &dp_regs->common_int_mask2);
 410
 411         reg = COMMON_INT_MASK_3;
 412         lwrite32(reg, &dp_regs->common_int_mask3);
 413
 414         reg = COMMON_INT_MASK_4;
 415         lwrite32(reg, &dp_regs->common_int_mask4);
 416
 417         reg = INT_STA_MASK;
 418         lwrite32(reg, &dp_regs->int_sta_mask);
 419
 420         return;
 421 }
 422
 423 unsigned int exynos_dp_get_plug_in_status(void)
 424 {
 425         u32 reg;
 426
 427         reg = lread32(&dp_regs->sys_ctl3);
 428         if (reg & HPD_STATUS)
 429                 return 0;
 430
 431         return -1;
 432 }
 433
 434 unsigned int exynos_dp_detect_hpd(void)
 435 {
 436         int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
 437
 438         mdelay(2);
 439
 440         while (exynos_dp_get_plug_in_status() != 0) {
 441                 if (timeout_loop == 0)
 442                         return -1;
 443                 mdelay(1);
 444                 timeout_loop--;
 445         }
 446
 447         return EXYNOS_DP_SUCCESS;
 448 }
 449
 450 unsigned int exynos_dp_start_aux_transaction(void)
 451 {
 452         u32 reg;
 453         unsigned int ret = 0;
 454         unsigned int retry_cnt;
 455
 456         /* Enable AUX CH operation */
 457         reg = lread32(&dp_regs->aux_ch_ctl2);
 458         reg |= AUX_EN;
 459         lwrite32(reg, &dp_regs->aux_ch_ctl2);
 460
 461         retry_cnt = 10;
 462         while (retry_cnt) {
 463                 reg = lread32(&dp_regs->int_sta);
 464                 if (!(reg & RPLY_RECEIV)) {
 465                         if (retry_cnt == 0) {
 466                                 printk(BIOS_ERR, "DP Reply Timeout!!\n");
 467                                 ret = -1;
 468                                 return ret;
 469                         }
 470                         mdelay(1);
 471                         retry_cnt--;
 472                 } else
 473                         break;
 474         }
 475
 476         /* Clear interrupt source for AUX CH command reply */
 477         lwrite32(reg, &dp_regs->int_sta);
 478
 479         /* Clear interrupt source for AUX CH access error */
 480         reg = lread32(&dp_regs->int_sta);
 481         if (reg & AUX_ERR) {
 482                 printk(BIOS_ERR, "DP Aux Access Error\n");
 483                 lwrite32(AUX_ERR, &dp_regs->int_sta);
 484                 ret = -1;
 485                 return ret;
 486         }
 487
 488         /* Check AUX CH error access status */
 489         reg = lread32(&dp_regs->aux_ch_sta);
 490         if ((reg & AUX_STATUS_MASK) != 0) {
 491                 printk(BIOS_DEBUG, "DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
 492                 ret = -1;
 493                 return ret;
 494         }
 495         return EXYNOS_DP_SUCCESS;
 496 }
 497
 498 unsigned int exynos_dp_write_byte_to_dpcd(u32 reg_addr, u8 data)
 499 {
 500         u32 reg;
 501         unsigned int ret;
 502
 503         /* Clear AUX CH data buffer */
 504         reg = BUF_CLR;
 505         lwrite32(reg, &dp_regs->buffer_data_ctl);
 506
 507         /* Select DPCD device address */
 508         reg = AUX_ADDR_7_0(reg_addr);
 509         lwrite32(reg, &dp_regs->aux_addr_7_0);
 510         reg = AUX_ADDR_15_8(reg_addr);
 511         lwrite32(reg, &dp_regs->aux_addr_15_8);
 512         reg = AUX_ADDR_19_16(reg_addr);
 513         lwrite32(reg, &dp_regs->aux_addr_19_16);
 514
 515         /* Write data buffer */
 516         reg = data;
 517         lwrite32(reg, &dp_regs->buf_data0);
 518
 519         /*
 520          * Set DisplayPort transaction and write 1 byte
 521          * If bit 3 is 1, DisplayPort transaction.
 522          * If Bit 3 is 0, I2C transaction.
 523          */
 524         reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 525         lwrite32(reg, &dp_regs->aux_ch_ctl1);
 526
 527         /* Start AUX transaction */
 528         ret = exynos_dp_start_aux_transaction();
 529         if (ret != EXYNOS_DP_SUCCESS) {
 530                 printk(BIOS_ERR, "DP Aux transaction failed\n");
 531         }
 532
 533         return ret;
 534 }
 535
 536 unsigned int exynos_dp_read_byte_from_dpcd(u32 reg_addr,
 537                 unsigned char *data)
 538 {
 539         u32 reg;
 540         int retval;
 541
 542         /* Clear AUX CH data buffer */
 543         reg = BUF_CLR;
 544         lwrite32(reg, &dp_regs->buffer_data_ctl);
 545
 546         /* Select DPCD device address */
 547         reg = AUX_ADDR_7_0(reg_addr);
 548         lwrite32(reg, &dp_regs->aux_addr_7_0);
 549         reg = AUX_ADDR_15_8(reg_addr);
 550         lwrite32(reg, &dp_regs->aux_addr_15_8);
 551         reg = AUX_ADDR_19_16(reg_addr);
 552         lwrite32(reg, &dp_regs->aux_addr_19_16);
 553
 554         /*
 555          * Set DisplayPort transaction and read 1 byte
 556          * If bit 3 is 1, DisplayPort transaction.
 557          * If Bit 3 is 0, I2C transaction.
 558          */
 559         reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 560         lwrite32(reg, &dp_regs->aux_ch_ctl1);
 561
 562         /* Start AUX transaction */
 563         retval = exynos_dp_start_aux_transaction();
 564         if (retval != EXYNOS_DP_SUCCESS)
 565                 printk(BIOS_DEBUG, "DP Aux Transaction fail!\n");
 566
 567         /* Read data buffer */
 568         reg = lread32(&dp_regs->buf_data0);
 569         *data = (unsigned char)(reg & 0xff);
 570
 571         return retval;
 572 }
 573
 574 unsigned int exynos_dp_write_bytes_to_dpcd(u32 reg_addr,
 575                                 unsigned int count,
 576                                 unsigned char data[])
 577 {
 578         u32 reg;
 579         unsigned int start_offset;
 580         unsigned int cur_data_count;
 581         unsigned int cur_data_idx;
 582         unsigned int retry_cnt;
 583         unsigned int ret = 0;
 584
 585         /* Clear AUX CH data buffer */
 586         reg = BUF_CLR;
 587         lwrite32(reg, &dp_regs->buffer_data_ctl);
 588
 589         start_offset = 0;
 590         while (start_offset < count) {
 591                 /* Buffer size of AUX CH is 16 * 4bytes */
 592                 if ((count - start_offset) > 16)
 593                         cur_data_count = 16;
 594                 else
 595                         cur_data_count = count - start_offset;
 596
 597                 retry_cnt = 5;
 598                 while (retry_cnt) {
 599                         /* Select DPCD device address */
 600                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 601                         lwrite32(reg, &dp_regs->aux_addr_7_0);
 602                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 603                         lwrite32(reg, &dp_regs->aux_addr_15_8);
 604                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 605                         lwrite32(reg, &dp_regs->aux_addr_19_16);
 606
 607                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 608                                         cur_data_idx++) {
 609                                 reg = data[start_offset + cur_data_idx];
 610                                 lwrite32(reg, (void *)((unsigned int)&dp_regs->buf_data0 +
 611                                                       (4 * cur_data_idx)));
 612                         }
 613                         /*
 614                         * Set DisplayPort transaction and write
 615                         * If bit 3 is 1, DisplayPort transaction.
 616                         * If Bit 3 is 0, I2C transaction.
 617                         */
 618                         reg = AUX_LENGTH(cur_data_count) |
 619                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 620                         lwrite32(reg, &dp_regs->aux_ch_ctl1);
 621
 622                         /* Start AUX transaction */
 623                         ret = exynos_dp_start_aux_transaction();
 624                         if (ret != EXYNOS_DP_SUCCESS) {
 625                                 if (retry_cnt == 0) {
 626                                         printk(BIOS_ERR, "DP Aux Transaction failed\n");
 627                                         return ret;
 628                                 }
 629                                 retry_cnt--;
 630                         } else
 631                                 break;
 632                 }
 633                 start_offset += cur_data_count;
 634         }
 635
 636         return ret;
 637 }
 638
 639 unsigned int exynos_dp_read_bytes_from_dpcd(u32 reg_addr,
 640                                 unsigned int count,
 641                                 unsigned char data[])
 642 {
 643         u32 reg;
 644         unsigned int start_offset;
 645         unsigned int cur_data_count;
 646         unsigned int cur_data_idx;
 647         unsigned int retry_cnt;
 648         unsigned int ret = 0;
 649
 650         /* Clear AUX CH data buffer */
 651         reg = BUF_CLR;
 652         lwrite32(reg, &dp_regs->buffer_data_ctl);
 653
 654         start_offset = 0;
 655         while (start_offset < count) {
 656                 /* Buffer size of AUX CH is 16 * 4bytes */
 657                 if ((count - start_offset) > 16)
 658                         cur_data_count = 16;
 659                 else
 660                         cur_data_count = count - start_offset;
 661
 662                 retry_cnt = 5;
 663                 while (retry_cnt) {
 664                         /* Select DPCD device address */
 665                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 666                         lwrite32(reg, &dp_regs->aux_addr_7_0);
 667                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 668                         lwrite32(reg, &dp_regs->aux_addr_15_8);
 669                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 670                         lwrite32(reg, &dp_regs->aux_addr_19_16);
 671                         /*
 672                          * Set DisplayPort transaction and read
 673                          * If bit 3 is 1, DisplayPort transaction.
 674                          * If Bit 3 is 0, I2C transaction.
 675                          */
 676                         reg = AUX_LENGTH(cur_data_count) |
 677                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 678                         lwrite32(reg, &dp_regs->aux_ch_ctl1);
 679
 680                         /* Start AUX transaction */
 681                         ret = exynos_dp_start_aux_transaction();
 682                         if (ret != EXYNOS_DP_SUCCESS) {
 683                                 if (retry_cnt == 0) {
 684                                         printk(BIOS_ERR, "DP Aux Transaction failed\n");
 685                                         return ret;
 686                                 }
 687                                 retry_cnt--;
 688                         } else
 689                                 break;
 690                 }
 691
 692                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 693                                 cur_data_idx++) {
 694                         reg = lread32((void *)((u32)&dp_regs->buf_data0 +
 695                                               4 * cur_data_idx));
 696                         data[start_offset + cur_data_idx] = (unsigned char)reg;
 697                 }
 698
 699                 start_offset += cur_data_count;
 700         }
 701
 702         return ret;
 703 }
 704
 705 int exynos_dp_select_i2c_device(u32 device_addr,
 706                                 u32 reg_addr)
 707 {
 708         u32 reg;
 709         int retval;
 710
 711         /* Set EDID device address */
 712         reg = device_addr;
 713         lwrite32(reg, &dp_regs->aux_addr_7_0);
 714         lwrite32(0x0, &dp_regs->aux_addr_15_8);
 715         lwrite32(0x0, &dp_regs->aux_addr_19_16);
 716
 717         /* Set offset from base address of EDID device */
 718         lwrite32(reg_addr, &dp_regs->buf_data0);
 719
 720         /*
 721          * Set I2C transaction and write address
 722          * If bit 3 is 1, DisplayPort transaction.
 723          * If Bit 3 is 0, I2C transaction.
 724          */
 725         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 726                 AUX_TX_COMM_WRITE;
 727         lwrite32(reg, &dp_regs->aux_ch_ctl1);
 728
 729         /* Start AUX transaction */
 730         retval = exynos_dp_start_aux_transaction();
 731         if (retval != 0)
 732                 printk(BIOS_DEBUG, "%s: DP Aux Transaction fail!\n", __func__);
 733
 734         return retval;
 735 }
 736
 737 int exynos_dp_read_byte_from_i2c(u32 device_addr,
 738                                 u32 reg_addr,
 739                                 unsigned int *data)
 740 {
 741         u32 reg;
 742         int i;
 743         int retval;
 744
 745         for (i = 0; i < 10; i++) {
 746                 /* Clear AUX CH data buffer */
 747                 reg = BUF_CLR;
 748                 lwrite32(reg, &dp_regs->buffer_data_ctl);
 749
 750                 /* Select EDID device */
 751                 retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
 752                 if (retval != 0) {
 753                         printk(BIOS_DEBUG, "DP Select EDID device fail. retry !\n");
 754                         continue;
 755                 }
 756
 757                 /*
 758                  * Set I2C transaction and read data
 759                  * If bit 3 is 1, DisplayPort transaction.
 760                  * If Bit 3 is 0, I2C transaction.
 761                  */
 762                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 763                         AUX_TX_COMM_READ;
 764                 lwrite32(reg, &dp_regs->aux_ch_ctl1);
 765
 766                 /* Start AUX transaction */
 767                 retval = exynos_dp_start_aux_transaction();
 768                 if (retval != EXYNOS_DP_SUCCESS)
 769                         printk(BIOS_DEBUG, "%s: DP Aux Transaction fail!\n", __func__);
 770         }
 771
 772         /* Read data */
 773         if (retval == 0)
 774                 *data = lread32(&dp_regs->buf_data0);
 775
 776         return retval;
 777 }
 778
 779 int exynos_dp_read_bytes_from_i2c(u32 device_addr,
 780                 u32 reg_addr, unsigned int count, unsigned char edid[])
 781 {
 782         u32 reg;
 783         unsigned int i, j;
 784         unsigned int cur_data_idx;
 785         unsigned int defer = 0;
 786         int retval = 0;
 787
 788         for (i = 0; i < count; i += 16) { /* use 16 burst */
 789                 for (j = 0; j < 100; j++) {
 790                         /* Clear AUX CH data buffer */
 791                         reg = BUF_CLR;
 792                         lwrite32(reg, &dp_regs->buffer_data_ctl);
 793
 794                         /* Set normal AUX CH command */
 795                         reg = lread32(&dp_regs->aux_ch_ctl2);
 796                         reg &= ~ADDR_ONLY;
 797                         lwrite32(reg, &dp_regs->aux_ch_ctl2);
 798
 799                         /*
 800                          * If Rx sends defer, Tx sends only reads
 801                          * request without sending address
 802                          */
 803                         if (!defer)
 804                                 retval =
 805                                         exynos_dp_select_i2c_device(device_addr,
 806                                                         reg_addr + i);
 807                         else
 808                                 defer = 0;
 809
 810                         if (retval == EXYNOS_DP_SUCCESS) {
 811                                 /*
 812                                  * Set I2C transaction and write data
 813                                  * If bit 3 is 1, DisplayPort transaction.
 814                                  * If Bit 3 is 0, I2C transaction.
 815                                  */
 816                                 reg = AUX_LENGTH(16) |
 817                                         AUX_TX_COMM_I2C_TRANSACTION |
 818                                         AUX_TX_COMM_READ;
 819                                 lwrite32(reg, &dp_regs->aux_ch_ctl1);
 820
 821                                 /* Start AUX transaction */
 822                                 retval = exynos_dp_start_aux_transaction();
 823                                 if (retval == 0)
 824                                         break;
 825                                 else
 826                                         printk(BIOS_ERR, "DP Aux Transaction fail!\n");
 827                         }
 828                         /* Check if Rx sends defer */
 829                         reg = lread32(&dp_regs->aux_rx_comm);
 830                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 831                                 reg == AUX_RX_COMM_I2C_DEFER) {
 832                                 printk(BIOS_ERR, "DP Defer: %d\n\n", reg);
 833                                 defer = 1;
 834                         }
 835                 }
 836
 837                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 838                         reg = lread32((void *)((u32)&dp_regs->buf_data0
 839                                               + 4 * cur_data_idx));
 840                         edid[i + cur_data_idx] = (unsigned char)reg;
 841                 }
 842         }
 843
 844         return retval;
 845 }
 846
 847 void exynos_dp_reset_macro(void)
 848 {
 849         u32 reg;
 850
 851         reg = lread32(&dp_regs->phy_test);
 852         reg |= MACRO_RST;
 853         lwrite32(reg, &dp_regs->phy_test);
 854
 855         /* 10 us is the minimum Macro reset time. */
 856         udelay(50);
 857
 858         reg &= ~MACRO_RST;
 859         lwrite32(reg, &dp_regs->phy_test);
 860 }
 861
 862 void exynos_dp_set_link_bandwidth(unsigned char bwtype)
 863 {
 864         u32 reg;
 865
 866         reg = (u32)bwtype;
 867
 868          /* Set bandwidth to 2.7G or 1.62G */
 869         if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
 870                 lwrite32(reg, &dp_regs->link_bw_set);
 871 }
 872
 873 unsigned char exynos_dp_get_link_bandwidth(void)
 874 {
 875         unsigned char ret;
 876         u32 reg;
 877
 878         reg = lread32(&dp_regs->link_bw_set);
 879         ret = (unsigned char)reg;
 880
 881         return ret;
 882 }
 883
 884 void exynos_dp_set_lane_count(unsigned char count)
 885 {
 886         u32 reg;
 887
 888         reg = (u32)count;
 889
 890         if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
 891                         (count == DP_LANE_CNT_4))
 892                 lwrite32(reg, &dp_regs->lane_count_set);
 893 }
 894
 895 unsigned int exynos_dp_get_lane_count(void)
 896 {
 897         u32 reg;
 898
 899         reg = lread32(&dp_regs->lane_count_set);
 900
 901         return reg;
 902 }
 903
 904 unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
 905 {
 906         void *reg_list[DP_LANE_CNT_4] = {
 907                 &dp_regs->ln0_link_training_ctl,
 908                 &dp_regs->ln1_link_training_ctl,
 909                 &dp_regs->ln2_link_training_ctl,
 910                 &dp_regs->ln3_link_training_ctl,
 911         };
 912
 913         return lread32(reg_list[lanecnt]);
 914 }
 915
 916 void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
 917                 unsigned char lanecnt)
 918 {
 919         void * reg_list[DP_LANE_CNT_4] = {
 920                 &dp_regs->ln0_link_training_ctl,
 921                 &dp_regs->ln1_link_training_ctl,
 922                 &dp_regs->ln2_link_training_ctl,
 923                 &dp_regs->ln3_link_training_ctl,
 924         };
 925
 926         lwrite32(request_val, reg_list[lanecnt]);
 927 }
 928
 929 void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
 930 {
 931         unsigned char i;
 932         u32 reg;
 933         void *reg_list[DP_LANE_CNT_4] = {
 934                 &dp_regs->ln0_link_training_ctl,
 935                 &dp_regs->ln1_link_training_ctl,
 936                 &dp_regs->ln2_link_training_ctl,
 937                 &dp_regs->ln3_link_training_ctl,
 938         };
 939         u32 reg_shift[DP_LANE_CNT_4] = {
 940                 PRE_EMPHASIS_SET_0_SHIFT,
 941                 PRE_EMPHASIS_SET_1_SHIFT,
 942                 PRE_EMPHASIS_SET_2_SHIFT,
 943                 PRE_EMPHASIS_SET_3_SHIFT
 944         };
 945
 946         for (i = 0; i < lanecnt; i++) {
 947                 reg = level << reg_shift[i];
 948                 lwrite32(reg, reg_list[i]);
 949         }
 950 }
 951
 952 void exynos_dp_set_training_pattern(unsigned int pattern)
 953 {
 954         u32 reg = 0;
 955
 956         switch (pattern) {
 957         case PRBS7:
 958                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 959                 break;
 960         case D10_2:
 961                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 962                 break;
 963         case TRAINING_PTN1:
 964                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 965                 break;
 966         case TRAINING_PTN2:
 967                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 968                 break;
 969         case DP_NONE:
 970                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
 971                         SW_TRAINING_PATTERN_SET_NORMAL;
 972                 break;
 973         default:
 974                 break;
 975         }
 976
 977         lwrite32(reg, &dp_regs->training_ptn_set);
 978 }
 979
 980 void exynos_dp_enable_enhanced_mode(unsigned char enable)
 981 {
 982         u32 reg;
 983
 984         reg = lread32(&dp_regs->sys_ctl4);
 985         reg &= ~ENHANCED;
 986
 987         if (enable)
 988                 reg |= ENHANCED;
 989
 990         lwrite32(reg, &dp_regs->sys_ctl4);
 991 }
 992
 993 void exynos_dp_enable_scrambling(unsigned int enable)
 994 {
 995         u32 reg;
 996
 997         reg = lread32(&dp_regs->training_ptn_set);
 998         reg &= ~(SCRAMBLING_DISABLE);
 999
1000         if (!enable)
1001                 reg |= SCRAMBLING_DISABLE;
1002
1003         lwrite32(reg, &dp_regs->training_ptn_set);
1004 }
1005 int exynos_dp_init_video(void)
1006 {
1007         unsigned int reg;
1008
1009         /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
1010         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1011         lwrite32(reg, &dp_regs->common_int_sta1);
1012
1013         /* I_STRM__CLK detect : DE_CTL : Auto detect */
1014         reg &= ~DET_CTRL;
1015         lwrite32(reg, &dp_regs->sys_ctl1);
1016         return 0;
1017 }
1018
1019
1020 void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
1021 {
1022         u32 reg;
1023
1024         /* Video Slave mode setting */
1025         reg = lread32(&dp_regs->func_en1);
1026         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1027         reg |= MASTER_VID_FUNC_EN_N;
1028         lwrite32(reg, &dp_regs->func_en1);
1029
1030         /* Configure Interlaced for slave mode video */
1031         reg = lread32(&dp_regs->video_ctl10);
1032         reg &= ~INTERACE_SCAN_CFG;
1033         reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
1034         printk(BIOS_SPEW, "interlaced %d\n", video_info->interlaced);
1035         lwrite32(reg, &dp_regs->video_ctl10);
1036
1037         /* Configure V sync polarity for slave mode video */
1038         reg = lread32(&dp_regs->video_ctl10);
1039         reg &= ~VSYNC_POLARITY_CFG;
1040         reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
1041         lwrite32(reg, &dp_regs->video_ctl10);
1042
1043         /* Configure H sync polarity for slave mode video */
1044         reg = lread32(&dp_regs->video_ctl10);
1045         reg &= ~HSYNC_POLARITY_CFG;
1046         reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1047         lwrite32(reg, &dp_regs->video_ctl10);
1048
1049         /*Set video mode to slave mode */
1050         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1051         lwrite32(reg, &dp_regs->soc_general_ctl);
1052 }
1053
1054 void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
1055 {
1056         u32 reg;
1057
1058         /* Configure the input color depth, color space, dynamic range */
1059         reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1060                 (video_info->color_depth << IN_BPC_SHIFT) |
1061                 (video_info->color_space << IN_COLOR_F_SHIFT);
1062         lwrite32(reg, &dp_regs->video_ctl2);
1063
1064         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1065         reg = lread32(&dp_regs->video_ctl3);
1066         reg &= ~IN_YC_COEFFI_MASK;
1067         if (video_info->ycbcr_coeff)
1068                 reg |= IN_YC_COEFFI_ITU709;
1069         else
1070                 reg |= IN_YC_COEFFI_ITU601;
1071         lwrite32(reg, &dp_regs->video_ctl3);
1072 }
1073
1074 unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
1075 {
1076         u32 reg;
1077
1078         /* Update Video stream clk detect status */
1079         reg = lread32(&dp_regs->sys_ctl1);
1080         lwrite32(reg, &dp_regs->sys_ctl1);
1081
1082         reg = lread32(&dp_regs->sys_ctl1);
1083
1084         if (!(reg & DET_STA)) {
1085                 printk(BIOS_DEBUG, "DP Input stream clock not detected.\n");
1086                 return -1;
1087         }
1088
1089         return EXYNOS_DP_SUCCESS;
1090 }
1091
1092 void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
1093                 unsigned int n_value)
1094 {
1095         u32 reg;
1096
1097         if (type == REGISTER_M) {
1098                 reg = lread32(&dp_regs->sys_ctl4);
1099                 reg |= FIX_M_VID;
1100                 lwrite32(reg, &dp_regs->sys_ctl4);
1101                 reg = M_VID0_CFG(m_value);
1102                 lwrite32(reg, &dp_regs->m_vid0);
1103                 reg = M_VID1_CFG(m_value);
1104                 lwrite32(reg, &dp_regs->m_vid1);
1105                 reg = M_VID2_CFG(m_value);
1106                 lwrite32(reg, &dp_regs->m_vid2);
1107
1108                 reg = N_VID0_CFG(n_value);
1109                 lwrite32(reg, &dp_regs->n_vid0);
1110                 reg = N_VID1_CFG(n_value);
1111                 lwrite32(reg, &dp_regs->n_vid1);
1112                 reg = N_VID2_CFG(n_value);
1113                 lwrite32(reg, &dp_regs->n_vid2);
1114         } else  {
1115                 reg = lread32(&dp_regs->sys_ctl4);
1116                 reg &= ~FIX_M_VID;
1117                 lwrite32(reg, &dp_regs->sys_ctl4);
1118         }
1119 }
1120
1121 void exynos_dp_set_video_timing_mode(unsigned int type)
1122 {
1123         u32 reg;
1124
1125         reg = lread32(&dp_regs->video_ctl10);
1126         reg &= ~FORMAT_SEL;
1127
1128         if (type != VIDEO_TIMING_FROM_CAPTURE)
1129                 reg |= FORMAT_SEL;
1130
1131         lwrite32(reg, &dp_regs->video_ctl10);
1132 }
1133
1134 void exynos_dp_enable_video_master(unsigned int enable)
1135 {
1136         u32 reg;
1137
1138         reg = lread32(&dp_regs->soc_general_ctl);
1139         if (enable) {
1140                 reg &= ~VIDEO_MODE_MASK;
1141                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1142         } else {
1143                 reg &= ~VIDEO_MODE_MASK;
1144                 reg |= VIDEO_MODE_SLAVE_MODE;
1145         }
1146
1147         lwrite32(reg, &dp_regs->soc_general_ctl);
1148 }
1149
1150 void exynos_dp_start_video(void)
1151 {
1152         u32 reg;
1153
1154         /* Enable Video input and disable Mute */
1155         reg = lread32(&dp_regs->video_ctl1);
1156         reg |= VIDEO_EN;
1157         lwrite32(reg, &dp_regs->video_ctl1);
1158 }
1159
1160 unsigned int exynos_dp_is_video_stream_on(void)
1161 {
1162         u32 reg;
1163
1164         /* Update STRM_VALID */
1165         reg = lread32(&dp_regs->sys_ctl3);
1166         lwrite32(reg, &dp_regs->sys_ctl3);
1167
1168         reg = lread32(&dp_regs->sys_ctl3);
1169
1170         if (!(reg & STRM_VALID))
1171                 return -1;
1172
1173         return EXYNOS_DP_SUCCESS;
1174 }
1175
1176 void dp_phy_control(unsigned int enable)
1177 {
1178         u32 cfg;
1179
1180         cfg = lread32(&exynos_power->dptx_phy_control);
1181         if (enable)
1182                 cfg |= EXYNOS_DP_PHY_ENABLE;
1183         else
1184                 cfg &= ~EXYNOS_DP_PHY_ENABLE;
1185         lwrite32(cfg, &exynos_power->dptx_phy_control);
1186 }