src/soc/samsung/exynos5420/cpu.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2013 Google Inc.
   5  * Copyright (C) 2012 Samsung Electronics
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/cache.h>
  18 #include <cbmem.h>
  19 #include <console/console.h>
  20 #include <delay.h>
  21 #include <device/device.h>
  22 #include <ec/google/chromeec/ec.h>
  23 #include <soc/dp.h>
  24 #include <soc/fimd.h>
  25 #include <soc/cpu.h>
  26 #include <soc/clk.h>
  27 #include <stddef.h>
  28 #include <stdlib.h>
  29 #include <string.h>
  30
  31 #include "chip.h"
  32
  33 static unsigned int cpu_id;
  34 static unsigned int cpu_rev;
  35
  36 static void set_cpu_id(void)
  37 {
  38         u32 pro_id = (read32((void *)EXYNOS5_PRO_ID) & 0x00FFF000) >> 12;
  39
  40         switch (pro_id) {
  41         case 0x200:
  42                 /* Exynos4210 EVT0 */
  43                 cpu_id = 0x4210;
  44                 cpu_rev = 0;
  45                 break;
  46         case 0x210:
  47                 /* Exynos4210 EVT1 */
  48                 cpu_id = 0x4210;
  49                 break;
  50         case 0x412:
  51                 /* Exynos4412 */
  52                 cpu_id = 0x4412;
  53                 break;
  54         case 0x520:
  55                 /* Exynos5250 */
  56                 cpu_id = 0x5250;
  57                 break;
  58         case 0x420:
  59                 /* Exynos5420 */
  60                 cpu_id = 0x5420;
  61                 break;
  62         }
  63 }
  64
  65 /* we distinguish a display port device from a raw graphics device
  66  * because there are dramatic differences in startup depending on
  67  * graphics usage. To make startup fast and easier to understand and
  68  * debug we explicitly name this common case. The alternate approach,
  69  * involving lots of machine and callbacks, is hard to debug and
  70  * verify.
  71  */
  72 static void exynos_displayport_init(device_t dev, u32 lcdbase,
  73                 unsigned long fb_size)
  74 {
  75         struct soc_samsung_exynos5420_config *conf = dev->chip_info;
  76         /* put these on the stack. If, at some point, we want to move
  77          * this code to a pre-ram stage, it will be much easier.
  78          */
  79         struct exynos5_fimd_panel panel;
  80         memset(&panel, 0, sizeof(panel));
  81
  82         panel.is_dp = 1; /* Display I/F is eDP */
  83         /* while it is true that we did a memset to zero,
  84          * we leave some 'set to zero' entries here to make
  85          * it clear what's going on. Graphics is confusing.
  86          */
  87         panel.is_mipi = 0;
  88         panel.fixvclk = 0;
  89         panel.ivclk = 0;
  90         panel.clkval_f = conf->clkval_f;
  91         panel.upper_margin = conf->upper_margin;
  92         panel.lower_margin = conf->lower_margin;
  93         panel.vsync = conf->vsync;
  94         panel.left_margin = conf->left_margin;
  95         panel.right_margin = conf->right_margin;
  96         panel.hsync = conf->hsync;
  97         panel.xres = conf->xres;
  98         panel.yres = conf->yres;
  99
 100         printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase));
 101         memset((void *)lcdbase, 0, fb_size);    /* clear the framebuffer */
 102
 103         /*
 104          * We need to clean and invalidate the framebuffer region and disable
 105          * caching as well. We assume that our dcache <--> memory address
 106          * space is identity-mapped in 1MB chunks, so align accordingly.
 107          *
 108          * Note: We may want to do something clever to ensure the framebuffer
 109          * region is aligned such that we don't change dcache policy for other
 110          * stuff inadvertently.
 111          */
 112         uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
 113         uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
 114
 115         dcache_clean_invalidate_by_mva((void *)lower, upper - lower);
 116         mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);
 117
 118         mmio_resource(dev, 1, lcdbase/KiB, CEIL_DIV(fb_size, KiB));
 119 }
 120
 121 static void tps65090_thru_ec_fet_disable(int index)
 122 {
 123         uint8_t value = 0;
 124
 125         if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) {
 126                 printk(BIOS_ERR,
 127                        "Error sending i2c pass through command to EC.\n");
 128                 return;
 129         }
 130 }
 131
 132 static void cpu_enable(device_t dev)
 133 {
 134         unsigned long fb_size = FB_SIZE_KB * KiB;
 135         u32 lcdbase = get_fb_base_kb() * KiB;
 136
 137         ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB);
 138         mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB));
 139
 140         /*
 141          * Disable LCD FETs before we do anything with the display.
 142          * FIXME(dhendrix): This is a gross hack and should be done
 143          * elsewhere (romstage?).
 144          */
 145         tps65090_thru_ec_fet_disable(1);
 146         tps65090_thru_ec_fet_disable(6);
 147
 148         exynos_displayport_init(dev, lcdbase, fb_size);
 149
 150         set_cpu_id();
 151 }
 152
 153 static void cpu_init(device_t dev)
 154 {
 155         printk(BIOS_INFO, "CPU:   S5P%X @ %ldMHz\n",
 156                         cpu_id, get_arm_clk() / 1000000);
 157 }
 158
 159 static struct device_operations cpu_ops = {
 160         .read_resources   = DEVICE_NOOP,
 161         .set_resources    = DEVICE_NOOP,
 162         .enable_resources = cpu_enable,
 163         .init             = cpu_init,
 164         .scan_bus         = 0,
 165 };
 166
 167 static void enable_exynos5420_dev(device_t dev)
 168 {
 169         dev->ops = &cpu_ops;
 170 }
 171
 172 struct chip_operations soc_samsung_exynos5420_ops = {
 173         CHIP_NAME("SOC Samsung Exynos 5420")
 174         .enable_dev = enable_exynos5420_dev,
 175 };