src/soc/samsung/exynos5250/alternate_cbfs.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2013 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16
  17 #include <assert.h>
  18 #include <boot_device.h>
  19 #include <cbfs.h>  /* This driver serves as a CBFS media source. */
  20 #include <console/console.h>
  21 #include <soc/alternate_cbfs.h>
  22 #include <soc/power.h>
  23 #include <soc/spi.h>
  24 #include <stdlib.h>
  25 #include <string.h>
  26 #include <symbols.h>
  27
  28 /* This allows USB A-A firmware upload from a compatible host in four parts:
  29  * The first two are the bare BL1 and the Coreboot boot block, which are just
  30  * written to their respective loading addresses. These transfers are initiated
  31  * by the IROM / BL1, so this code has nothing to do with them.
  32  *
  33  * The third transfer is a valid CBFS image that contains only the romstage,
  34  * and must be small enough to fit into the PRE_RAM CBFS cache in
  35  * IRAM. It is loaded when this function gets called in the boot block, and
  36  * the normal CBFS code extracts the romstage from it.
  37  *
  38  * The fourth transfer is also a CBFS image, but can be of arbitrary size and
  39  * should contain all available stages/payloads/etc. It is loaded when this
  40  * function is called a second time at the end of the romstage, and copied to
  41  * the romstage/ramstage CBFS cache in DRAM. It will reside there for the
  42  * rest of the firmware's lifetime and all subsequent stages (which will not
  43  * have __PRE_RAM__ defined) can just directly reference it there.
  44  */
  45 static int usb_cbfs_open(void)
  46 {
  47 #ifdef __PRE_RAM__
  48         static int first_run = 1;
  49         int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr;
  50
  51         if (!first_run)
  52                 return 0;
  53
  54         if (!irom_load_usb()) {
  55                 printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n");
  56                 return -1;
  57         }
  58
  59         /*
  60          * We need to trust the host/irom to copy the image to our
  61          * _cbfs_cache address... there is no way to control or even
  62          * check the transfer size or target address from our side.
  63          */
  64
  65         printk(BIOS_DEBUG, "USB A-A transfer successful, CBFS image should now"
  66                 " be at %p\n", _cbfs_cache);
  67         first_run = 0;
  68 #endif
  69         return 0;
  70 }
  71
  72 /*
  73  * SDMMC works very similar to USB A-A: we copy the CBFS image into memory
  74  * and read it from there. While SDMMC would also allow direct block by block
  75  * on-demand reading, we might run into problems if we call back into the IROM
  76  * in very late boot stages (e.g. after initializing/changing MMC clocks)... so
  77  * this seems like a safer approach. It also makes it easy to pass our image
  78  * down to payloads.
  79  */
  80 static int sdmmc_cbfs_open(void)
  81 {
  82 #ifdef __PRE_RAM__
  83         /*
  84          * In the bootblock, we just copy the small part that fits in the buffer
  85          * and hope that it's enough (since the romstage is currently always the
  86          * first component in the image, this should work out). In the romstage,
  87          * we copy until our cache is full (currently 12M) to avoid the pain of
  88          * figuring out the true image size from in here. Since this is mainly a
  89          * developer/debug boot mode, those shortcomings should be bearable.
  90          */
  91         const u32 count = _cbfs_cache_size / 512;
  92         static int first_run = 1;
  93         int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
  94                 *irom_sdmmc_read_blocks_ptr;
  95
  96         if (!first_run)
  97                 return 0;
  98
  99         if (!irom_load_sdmmc(1, count, _cbfs_cache)) {
 100                 printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n");
 101                 return -1;
 102         }
 103
 104         printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be"
 105                 " at %p\n", _cbfs_cache);
 106         first_run = 0;
 107 #endif
 108         return 0;
 109 }
 110
 111 static struct mem_region_device alternate_rdev = MEM_REGION_DEV_INIT(NULL, 0);
 112
 113 const struct region_device *boot_device_ro(void)
 114 {
 115         if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
 116                 return &alternate_rdev.rdev;
 117
 118         switch (exynos_power->om_stat & OM_STAT_MASK) {
 119         case OM_STAT_SDMMC:
 120                 return &alternate_rdev.rdev;
 121         case OM_STAT_SPI:
 122                 return exynos_spi_boot_device();
 123         default:
 124                 printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
 125                         exynos_power->om_stat);
 126                 return NULL;
 127         }
 128 }
 129
 130 void boot_device_init(void)
 131 {
 132         mem_region_device_init(&alternate_rdev, _cbfs_cache, _cbfs_cache_size);
 133
 134         if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) {
 135                 printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
 136                 usb_cbfs_open();
 137                 return;
 138         }
 139
 140         switch (exynos_power->om_stat & OM_STAT_MASK) {
 141         case OM_STAT_SDMMC:
 142                 printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
 143                 sdmmc_cbfs_open();
 144                 break;
 145         case OM_STAT_SPI:
 146                 exynos_init_spi_boot_device();
 147                 break;
 148         default:
 149                 printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
 150                         exynos_power->om_stat);
 151         }
 152 }