src/soc/nvidia/tegra210/flow_ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/io.h>
  17 #include <soc/addressmap.h>
  18 #include <soc/flow_ctrl.h>
  19
  20 #define FLOW_CTRL_HALT_CPU0_EVENTS      0x0
  21 #define FLOW_CTRL_WAITEVENT             (2 << 29)
  22 #define FLOW_CTRL_WAIT_FOR_INTERRUPT    (4 << 29)
  23 #define FLOW_CTRL_HALT_SCLK             (1 << 27)
  24 #define FLOW_CTRL_HALT_LIC_IRQ          (1 << 11)
  25 #define FLOW_CTRL_HALT_LIC_FIQ          (1 << 10)
  26 #define FLOW_CTRL_HALT_GIC_IRQ          (1 << 9)
  27 #define FLOW_CTRL_HALT_GIC_FIQ          (1 << 8)
  28 #define FLOW_CTRL_CPU0_CSR              0x8
  29 #define FLOW_CTRL_CSR_INTR_FLAG         (1 << 15)
  30 #define FLOW_CTRL_CSR_EVENT_FLAG        (1 << 14)
  31 #define FLOW_CTRL_CSR_WFI_CPU0          (1 << 8)
  32 #define FLOW_CTRL_CSR_WFI_BITMAP        (0xF << 8)
  33 #define FLOW_CTRL_CSR_WFE_BITMAP        (0xF << 4)
  34 #define FLOW_CTRL_CSR_ENABLE            (1 << 0)
  35 #define FLOW_CTRL_HALT_CPU1_EVENTS      0x14
  36 #define FLOW_CTRL_CPU1_CSR              0x18
  37 #define FLOW_CTRL_CC4_CORE0_CTRL        0x6c
  38
  39 static void *tegra_flowctrl_base = (void*)TEGRA_FLOW_BASE;
  40
  41 static const uint8_t flowctrl_offset_halt_cpu[] = {
  42         FLOW_CTRL_HALT_CPU0_EVENTS,
  43         FLOW_CTRL_HALT_CPU1_EVENTS,
  44         FLOW_CTRL_HALT_CPU1_EVENTS + 8,
  45         FLOW_CTRL_HALT_CPU1_EVENTS + 16
  46 };
  47
  48 static const uint8_t flowctrl_offset_cpu_csr[] = {
  49         FLOW_CTRL_CPU0_CSR,
  50         FLOW_CTRL_CPU1_CSR,
  51         FLOW_CTRL_CPU1_CSR + 8,
  52         FLOW_CTRL_CPU1_CSR + 16
  53 };
  54
  55 static const uint8_t flowctrl_offset_cc4_ctrl[] = {
  56         FLOW_CTRL_CC4_CORE0_CTRL,
  57         FLOW_CTRL_CC4_CORE0_CTRL + 4,
  58         FLOW_CTRL_CC4_CORE0_CTRL + 8,
  59         FLOW_CTRL_CC4_CORE0_CTRL + 12
  60 };
  61
  62 void flowctrl_write_cpu_csr(int cpu, uint32_t val)
  63 {
  64         write32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu], val);
  65         val = read32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
  66 }
  67
  68 void flowctrl_write_cpu_halt(int cpu, uint32_t val)
  69 {
  70         write32(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu], val);
  71         val = read32(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]);
  72 }
  73
  74 void flowctrl_write_cc4_ctrl(int cpu, uint32_t val)
  75 {
  76         write32(tegra_flowctrl_base + flowctrl_offset_cc4_ctrl[cpu], val);
  77         val = read32(tegra_flowctrl_base + flowctrl_offset_cc4_ctrl[cpu]);
  78 }
  79
  80 void flowctrl_cpu_off(int cpu)
  81 {
  82         uint32_t val = FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG |
  83                 FLOW_CTRL_CSR_ENABLE | (FLOW_CTRL_CSR_WFI_CPU0 << cpu);
  84
  85         flowctrl_write_cpu_csr(cpu, val);
  86         flowctrl_write_cpu_halt(cpu, FLOW_CTRL_WAITEVENT);
  87         flowctrl_write_cc4_ctrl(cpu, 0);
  88 }
  89
  90 void flowctrl_cpu_on(int cpu)
  91 {
  92         flowctrl_write_cpu_csr(cpu, FLOW_CTRL_CSR_ENABLE);
  93         flowctrl_write_cpu_halt(cpu, FLOW_CTRL_WAITEVENT |
  94                                 FLOW_CTRL_HALT_SCLK);
  95 }
  96
  97 void flowctrl_cpu_suspend(int cpu)
  98 {
  99         uint32_t val;
 100
 101         val = FLOW_CTRL_HALT_GIC_IRQ | FLOW_CTRL_HALT_GIC_FIQ |
 102               FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ |
 103               FLOW_CTRL_WAITEVENT;
 104         flowctrl_write_cpu_halt(cpu, val);
 105
 106         val = FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG |
 107               FLOW_CTRL_CSR_ENABLE | (FLOW_CTRL_CSR_WFI_CPU0 << cpu);
 108         flowctrl_write_cpu_csr(cpu, val);
 109 }