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tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / soc / nvidia / tegra210 / dsi.c
blob3b771c9f4ef71fb35f8cae457106eef9b384a763
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <console/console.h>
16 #include <arch/io.h>
17 #include <stdint.h>
18 #include <lib.h>
19 #include <stdlib.h>
20 #include <delay.h>
21 #include <timer.h>
22 #include <soc/addressmap.h>
23 #include <soc/clock.h>
24 #include <device/device.h>
25 #include <edid.h>
26 #include <soc/nvidia/tegra/types.h>
27 #include <soc/nvidia/tegra/dc.h>
28 #include "chip.h"
29 #include <soc/display.h>
30 #include <soc/mipi_dsi.h>
31 #include <soc/mipi_display.h>
32 #include <soc/tegra_dsi.h>
33 #include <soc/mipi-phy.h>
34 #include "jdi_25x18_display/panel-jdi-lpm102a188a.h"
35
36 struct tegra_mipi_device mipi_device_data[NUM_DSI];
37
38 struct tegra_dsi dsi_data[NUM_DSI] = {
39 {
40 .regs = (void *)TEGRA_DSIA_BASE,
41 .channel = 0,
42 .slave = &dsi_data[DSI_B],
43 .master = NULL,
44 .video_fifo_depth = MAX_DSI_VIDEO_FIFO_DEPTH,
45 .host_fifo_depth = MAX_DSI_HOST_FIFO_DEPTH,
46 },
47 {
48 .regs = (void *)TEGRA_DSIB_BASE,
49 .channel = 0,
50 .slave = NULL,
51 .master = &dsi_data[DSI_A],
52 .video_fifo_depth = MAX_DSI_VIDEO_FIFO_DEPTH,
53 .host_fifo_depth = MAX_DSI_HOST_FIFO_DEPTH,
54 },
55 };
56
57 static const u32 init_reg[] = {
58 DSI_INT_ENABLE,
59 DSI_INT_STATUS,
60 DSI_INT_MASK,
61 DSI_INIT_SEQ_DATA_0,
62 DSI_INIT_SEQ_DATA_1,
63 DSI_INIT_SEQ_DATA_2,
64 DSI_INIT_SEQ_DATA_3,
65 DSI_INIT_SEQ_DATA_4,
66 DSI_INIT_SEQ_DATA_5,
67 DSI_INIT_SEQ_DATA_6,
68 DSI_INIT_SEQ_DATA_7,
69 DSI_INIT_SEQ_DATA_15,
70 DSI_DCS_CMDS,
71 DSI_PKT_SEQ_0_LO,
72 DSI_PKT_SEQ_1_LO,
73 DSI_PKT_SEQ_2_LO,
74 DSI_PKT_SEQ_3_LO,
75 DSI_PKT_SEQ_4_LO,
76 DSI_PKT_SEQ_5_LO,
77 DSI_PKT_SEQ_0_HI,
78 DSI_PKT_SEQ_1_HI,
79 DSI_PKT_SEQ_2_HI,
80 DSI_PKT_SEQ_3_HI,
81 DSI_PKT_SEQ_4_HI,
82 DSI_PKT_SEQ_5_HI,
83 DSI_CONTROL,
84 DSI_HOST_CONTROL,
85 DSI_PAD_CONTROL_0,
86 DSI_PAD_CONTROL_CD,
87 DSI_SOL_DELAY,
88 DSI_MAX_THRESHOLD,
89 DSI_TRIGGER,
90 DSI_TX_CRC,
91 DSI_INIT_SEQ_CONTROL,
92 DSI_PKT_LEN_0_1,
93 DSI_PKT_LEN_2_3,
94 DSI_PKT_LEN_4_5,
95 DSI_PKT_LEN_6_7,
96 };
97
98 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
99 {
100 return container_of(host, struct tegra_dsi, host);
101 }
102
103 /*
104 * non-burst mode with sync pulses
105 */
106 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
107 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
108 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
109 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
110 PKT_LP,
111 [ 1] = 0,
112 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
113 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
114 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
115 PKT_LP,
116 [ 3] = 0,
117 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
118 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
119 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
120 PKT_LP,
121 [ 5] = 0,
122 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
123 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
124 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
125 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
126 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
127 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
128 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
129 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
130 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
131 PKT_LP,
132 [ 9] = 0,
133 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
134 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
135 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
136 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
137 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
138 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
139 };
140
141 /*
142 * non-burst mode with sync events
143 */
144 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
145 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
146 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
147 PKT_LP,
148 [ 1] = 0,
149 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
150 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
151 PKT_LP,
152 [ 3] = 0,
153 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
154 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
155 PKT_LP,
156 [ 5] = 0,
157
158 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
159 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
160 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
161
162 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
163 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
164 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
165 PKT_LP,
166 [ 9] = 0,
167
168 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
169 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
170 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
171
172 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
173 };
174
175 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
176 [ 0] = 0,
177 [ 1] = 0,
178 [ 2] = 0,
179 [ 3] = 0,
180 [ 4] = 0,
181 [ 5] = 0,
182 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
183 [ 7] = 0,
184 [ 8] = 0,
185 [ 9] = 0,
186 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
187 [11] = 0,
188 };
189
190 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
191 {
192 int err;
193
194 err = mipi_dphy_set_timing(dsi);
195 if (err < 0) {
196 printk(BIOS_ERR, "failed to set D-PHY timing: %d\n", err);
197 return err;
198 }
199
200 if (dsi->slave)
201 tegra_dsi_set_phy_timing(dsi->slave);
202 return 0;
203 }
204
205 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
206 unsigned int *mulp, unsigned int *divp)
207 {
208 switch (format) {
209 case MIPI_DSI_FMT_RGB666_PACKED:
210 case MIPI_DSI_FMT_RGB888:
211 *mulp = 3;
212 *divp = 1;
213 break;
214
215 case MIPI_DSI_FMT_RGB565:
216 *mulp = 2;
217 *divp = 1;
218 break;
219
220 case MIPI_DSI_FMT_RGB666:
221 *mulp = 9;
222 *divp = 4;
223 break;
224
225 default:
226 return -EINVAL;
227 }
228 return 0;
229 }
230
231 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
232 enum tegra_dsi_format *fmt)
233 {
234 switch (format) {
235 case MIPI_DSI_FMT_RGB888:
236 *fmt = TEGRA_DSI_FORMAT_24P;
237 break;
238
239 case MIPI_DSI_FMT_RGB666:
240 *fmt = TEGRA_DSI_FORMAT_18NP;
241 break;
242
243 case MIPI_DSI_FMT_RGB666_PACKED:
244 *fmt = TEGRA_DSI_FORMAT_18P;
245 break;
246
247 case MIPI_DSI_FMT_RGB565:
248 *fmt = TEGRA_DSI_FORMAT_16P;
249 break;
250
251 default:
252 return -EINVAL;
253 }
254 return 0;
255 }
256
257 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
258 unsigned int size)
259 {
260 u32 value;
261
262 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
263 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
264
265 value = DSI_GANGED_MODE_CONTROL_ENABLE;
266 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
267 }
268
269 static void tegra_dsi_enable(struct tegra_dsi *dsi)
270 {
271 u32 value;
272
273 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
274 value |= DSI_POWER_CONTROL_ENABLE;
275 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
276
277 if (dsi->slave)
278 tegra_dsi_enable(dsi->slave);
279 }
280
281 static int tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
282 const struct soc_nvidia_tegra210_config *mode)
283 {
284 unsigned int hact, hsw, hbp, hfp, i, mul, div;
285 enum tegra_dsi_format format;
286 const u32 *pkt_seq;
287 u32 value;
288 int err;
289
290 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
291 printk(BIOS_SPEW, "Non-burst video mode with sync pulses\n");
292 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
293 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
294 printk(BIOS_SPEW, "Non-burst video mode with sync events\n");
295 pkt_seq = pkt_seq_video_non_burst_sync_events;
296 } else {
297 printk(BIOS_SPEW, "Command mode\n");
298 pkt_seq = pkt_seq_command_mode;
299 }
300
301 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
302 if (err < 0)
303 return err;
304
305 err = tegra_dsi_get_format(dsi->format, &format);
306 if (err < 0)
307 return err;
308
309 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
310 DSI_CONTROL_LANES(dsi->lanes - 1) |
311 DSI_CONTROL_SOURCE(pipe);
312 tegra_dsi_writel(dsi, value, DSI_CONTROL);
313
314 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
315
316 value = DSI_HOST_CONTROL_HS;
317 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
318
319 value = tegra_dsi_readl(dsi, DSI_CONTROL);
320
321 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
322 value |= DSI_CONTROL_HS_CLK_CTRL;
323
324 value &= ~DSI_CONTROL_TX_TRIG(3);
325
326 /* enable DCS commands for command mode */
327 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
328 value &= ~DSI_CONTROL_DCS_ENABLE;
329 else
330 value |= DSI_CONTROL_DCS_ENABLE;
331
332 value |= DSI_CONTROL_VIDEO_ENABLE;
333 value &= ~DSI_CONTROL_HOST_ENABLE;
334 tegra_dsi_writel(dsi, value, DSI_CONTROL);
335
336 for (i = 0; i < NUM_PKT_SEQ; i++)
337 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
338
339 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
340 /* horizontal active pixels */
341 hact = mode->xres * mul / div;
342
343 /* horizontal sync width */
344 hsw = (hsync_end(mode) - hsync_start(mode)) * mul / div;
345
346 /* horizontal back porch */
347 hbp = (htotal(mode) - hsync_end(mode)) * mul / div;
348 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
349 hbp += hsw;
350
351 /* horizontal front porch */
352 hfp = (hsync_start(mode) - mode->xres) * mul / div;
353
354 /* subtract packet overhead */
355 hsw -= 10;
356 hbp -= 14;
357 hfp -= 8;
358
359 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
360 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
361 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
362 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
363
364 /* set SOL delay (for non-burst mode only) */
365 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
366
367 /* TODO: implement ganged mode */
368 } else {
369 u16 bytes;
370 if (dsi->ganged_mode) {
371 /*
372 * For ganged mode, assume symmetric left-right mode.
373 */
374 bytes = 1 + (mode->xres / 2) * mul / div;
375 } else {
376 /* 1 byte (DCS command) + pixel data */
377 bytes = 1 + mode->xres * mul / div;
378 }
379
380 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
381 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
382 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
383 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
384
385 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
386 MIPI_DCS_WRITE_MEMORY_CONTINUE;
387 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
388
389 /* set SOL delay */
390 if (dsi->ganged_mode) {
391 unsigned long delay, bclk, bclk_ganged;
392 unsigned int lanes = dsi->ganged_lanes;
393
394 /* SOL to valid, valid to FIFO and FIFO write delay */
395 delay = 4 + 4 + 2;
396 delay = DIV_ROUND_UP(delay * mul, div * lanes);
397 /* FIFO read delay */
398 delay = delay + 6;
399
400 bclk = DIV_ROUND_UP(htotal(mode) * mul, div * lanes);
401 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
402 value = bclk - bclk_ganged + delay + 20;
403 } else {
404 /* TODO: revisit for non-ganged mode */
405 value = 8 * mul / div;
406 }
407
408 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
409 }
410
411 if (dsi->slave) {
412 err = tegra_dsi_configure(dsi->slave, pipe, mode);
413 if (err < 0)
414 return err;
415
416 /*
417 * enable ganged mode
418 */
419 if (dsi->ganged_mode) {
420 tegra_dsi_ganged_enable(dsi, mode->xres / 2,
421 mode->xres / 2);
422 tegra_dsi_ganged_enable(dsi->slave, 0, mode->xres / 2);
423 }
424 }
425 return 0;
426 }
427
428 static int tegra_output_dsi_enable(struct tegra_dsi *dsi,
429 const struct soc_nvidia_tegra210_config *config)
430 {
431 int err;
432
433 if (dsi->enabled)
434 return 0;
435
436 err = tegra_dsi_configure(dsi, 0, config);
437 if (err < 0) {
438 printk(BIOS_ERR, "DSI configuration failed\n");
439 return err;
440 }
441
442 /* enable DSI controller */
443 tegra_dsi_enable(dsi);
444
445 dsi->enabled = true;
446 return 0;
447 }
448
449
450 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
451 unsigned int vrefresh)
452 {
453 unsigned int timeout;
454 u32 value;
455
456 /* one frame high-speed transmission timeout */
457 timeout = (bclk / vrefresh) / 512;
458 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
459 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
460
461 /* 2 ms peripheral timeout for panel */
462 timeout = 2 * bclk / 512 * 1000;
463 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
464 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
465
466 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
467 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
468
469 if (dsi->slave)
470 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
471 }
472
473 static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi,
474 const struct soc_nvidia_tegra210_config *config)
475 {
476 unsigned int mul, div, num_lanes;
477 unsigned long bclk;
478 unsigned long pclk = config->pixel_clock;
479 int plld;
480 int err;
481 struct display_controller *disp_ctrl =
482 (void *)config->display_controller;
483 unsigned int shift_clk_div;
484
485 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
486 if (err < 0)
487 return err;
488
489 /*
490 * In ganged mode, account for the total number of lanes across both
491 * DSI channels so that the bit clock is properly computed.
492 */
493 if (dsi->ganged_mode)
494 num_lanes = dsi->ganged_lanes;
495 else
496 num_lanes = dsi->lanes;
497
498 /* compute byte clock */
499 bclk = (pclk * mul) / (div * num_lanes);
500
501 /*
502 * Compute bit clock and round up to the next MHz.
503 */
504 plld = DIV_ROUND_UP(bclk * 8, USECS_PER_SEC) * USECS_PER_SEC;
505
506 /*
507 * the actual rate on PLLD_OUT0 is 1/2 plld
508 */
509 dsi->clk_rate = plld / 2;
510 if (dsi->slave)
511 dsi->slave->clk_rate = dsi->clk_rate;
512
513 /* set up plld */
514 plld = clock_configure_plld(plld);
515 if (plld == 0) {
516 printk(BIOS_ERR, "%s: clock init failed\n", __func__);
517 return -1;
518 } else
519 printk(BIOS_INFO, "%s: plld is configured to: %u\n",
520 __func__, plld);
521
522 /*
523 * Derive pixel clock from bit clock using the shift clock divider.
524 * Note that this is only half of what we would expect, but we need
525 * that to make up for the fact that we divided the bit clock by a
526 * factor of two above.
527 */
528 shift_clk_div = ((8 * mul) / (div * num_lanes)) - 2;
529 update_display_shift_clock_divider(disp_ctrl, shift_clk_div);
530
531 tegra_dsi_set_timeout(dsi, bclk, config->refresh);
532 return plld/1000000;
533 }
534
535
536
537 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
538 {
539 unsigned long value;
540
541 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
542 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
543 return 0;
544 }
545
546 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
547 {
548 u32 value;
549
550 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
551 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
552 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
553 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
554 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
555
556 /* start calibration */
557 tegra_dsi_pad_enable(dsi);
558
559 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
560 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
561 DSI_PAD_OUT_CLK(0x0);
562 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
563
564 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
565 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
566 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
567
568 return tegra_mipi_calibrate(dsi->mipi);
569 }
570
571 static const char * const error_report[16] = {
572 "SoT Error",
573 "SoT Sync Error",
574 "EoT Sync Error",
575 "Escape Mode Entry Command Error",
576 "Low-Power Transmit Sync Error",
577 "Peripheral Timeout Error",
578 "False Control Error",
579 "Contention Detected",
580 "ECC Error, single-bit",
581 "ECC Error, multi-bit",
582 "Checksum Error",
583 "DSI Data Type Not Recognized",
584 "DSI VC ID Invalid",
585 "Invalid Transmission Length",
586 "Reserved",
587 "DSI Protocol Violation",
588 };
589
590 static int tegra_dsi_read_response(struct tegra_dsi *dsi,
591 const struct mipi_dsi_msg *msg,
592 unsigned int count)
593 {
594 u8 *rx = msg->rx_buf;
595 unsigned int i, j, k;
596 size_t size = 0;
597 u16 errors;
598 u32 value;
599
600 /* read and parse packet header */
601 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
602
603 switch (value & 0x3f) {
604 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
605 errors = (value >> 8) & 0xffff;
606 printk(BIOS_ERR, "Acknowledge and error report: %04x\n",
607 errors);
608 for (i = 0; i < ARRAY_SIZE(error_report); i++)
609 if (errors & BIT(i))
610 printk(BIOS_INFO, " %2u: %s\n", i,
611 error_report[i]);
612 break;
613
614 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
615 rx[0] = (value >> 8) & 0xff;
616 break;
617
618 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
619 rx[0] = (value >> 8) & 0xff;
620 rx[1] = (value >> 16) & 0xff;
621 break;
622
623 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
624 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
625 break;
626
627 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
628 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
629 break;
630
631 default:
632 printk(BIOS_ERR, "unhandled response type: %02x\n",
633 value & 0x3f);
634 break;
635 }
636
637 size = MIN(size, msg->rx_len);
638
639 if (msg->rx_buf && size > 0) {
640 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
641 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
642
643 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
644 rx[j + k] = (value >> (k << 3)) & 0xff;
645 }
646 }
647 return 0;
648 }
649
650 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout_ms)
651 {
652 u32 poll_interval_us = 2000;
653 u32 timeout_us = timeout_ms * 1000;
654
655 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
656 udelay(poll_interval_us);
657
658 do {
659 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
660 if ((value & DSI_TRIGGER_HOST) == 0)
661 return 0;
662
663 //usleep_range(1000, 2000);
664 if (timeout_us > poll_interval_us)
665 timeout_us -= poll_interval_us;
666 else
667 break;
668
669 udelay(poll_interval_us);
670 } while (1);
671
672 printk(BIOS_ERR, "%s: ERROR: timeout waiting for transmission"
673 " to complete\n", __func__);
674 return -ETIMEDOUT;
675 }
676
677 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
678 unsigned long timeout_ms)
679 {
680 u32 poll_interval_us = 2000;
681 u32 timeout_us = timeout_ms * 1000;
682
683 do {
684 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
685 u8 count = value & 0x1f;
686
687 if (count > 0)
688 return count;
689
690 if (timeout_us > poll_interval_us)
691 timeout_us -= poll_interval_us;
692 else
693 break;
694
695 udelay(poll_interval_us);
696 } while (1);
697
698 printk(BIOS_ERR, "%s: ERROR: timeout\n", __func__);
699
700 return -ETIMEDOUT;
701 }
702
703 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
704 const struct mipi_dsi_msg *msg)
705 {
706 struct tegra_dsi *dsi = host_to_tegra(host);
707 const u8 *tx = msg->tx_buf;
708 unsigned int count, i, j;
709 u32 value;
710 int err;
711
712 if (msg->tx_len > dsi->video_fifo_depth * 4)
713 return -ENOSPC;
714
715 /* reset underflow/overflow flags */
716 value = tegra_dsi_readl(dsi, DSI_STATUS);
717 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
718 value = DSI_HOST_CONTROL_FIFO_RESET;
719 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
720 udelay(20); // usleep_range(10, 20);
721 }
722
723 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
724 value |= DSI_POWER_CONTROL_ENABLE;
725 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
726
727 udelay(7000); //usleep_range(5000, 10000);
728
729 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
730 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
731
732 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
733 value |= DSI_HOST_CONTROL_HS;
734
735 /*
736 * The host FIFO has a maximum of 64 words, so larger transmissions
737 * need to use the video FIFO.
738 */
739 if (msg->tx_len > dsi->host_fifo_depth * 4)
740 value |= DSI_HOST_CONTROL_FIFO_SEL;
741
742 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
743
744 /*
745 * For reads and messages with explicitly requested ACK, generate a
746 * BTA sequence after the transmission of the packet.
747 */
748 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
749 (msg->rx_buf && msg->rx_len > 0)) {
750 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
751 value |= DSI_HOST_CONTROL_PKT_BTA;
752 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
753 }
754
755 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
756 tegra_dsi_writel(dsi, value, DSI_CONTROL);
757
758 /* write packet header */
759 value = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f);
760
761 if (tx && msg->tx_len > 0)
762 value |= tx[0] << 8;
763
764 if (tx && msg->tx_len > 1)
765 value |= tx[1] << 16;
766
767 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
768
769 /* write payload (if any) */
770 if (msg->tx_len > 2) {
771 for (j = 2; j < msg->tx_len; j += 4) {
772 value = 0;
773
774 for (i = 0; i < 4 && j + i < msg->tx_len; i++)
775 value |= tx[j + i] << (i << 3);
776
777 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
778 }
779 }
780
781 err = tegra_dsi_transmit(dsi, 250);
782 if (err < 0) {
783 printk(BIOS_INFO, "Failed to transmit. %d\n", err);
784 return err;
785 }
786
787 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
788 (msg->rx_buf && msg->rx_len > 0)) {
789 err = tegra_dsi_wait_for_response(dsi, 250);
790 if (err < 0) {
791 printk(BIOS_INFO, "Failed to read response. %d\n", err);
792 return err;
793 }
794 count = err;
795
796 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
797 switch (value) {
798 case 0x84:
799 printk(BIOS_INFO, "ACK\n");
800 break;
801
802 case 0x87:
803 printk(BIOS_INFO, "ESCAPE\n");
804 break;
805
806 default:
807 printk(BIOS_INFO, "unknown status: %08x\n", value);
808 break;
809 }
810
811 if (count > 1) {
812 err = tegra_dsi_read_response(dsi, msg, count);
813 if (err < 0)
814 printk(BIOS_INFO,
815 "failed to parse response: %d\n",
816 err);
817 else {
818 /*
819 * For read commands, return the number of
820 * bytes returned by the peripheral.
821 */
822 count = err;
823 }
824 }
825 } else {
826 /*
827 * For write commands, we have transmitted the 4-byte header
828 * plus the variable-length payload.
829 */
830 count = 4 + msg->tx_len;
831 }
832
833 return count;
834 }
835
836 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi,
837 struct tegra_dsi *slave)
838 {
839 /*
840 * The number of ganged lanes is the sum of lanes of all peripherals
841 * in the gang.
842 */
843 dsi->slave->ganged_lanes = dsi->lanes + dsi->slave->lanes;
844 dsi->slave->ganged_mode = 1;
845
846 dsi->ganged_lanes = dsi->lanes + dsi->slave->lanes;
847 dsi->ganged_mode = 1;
848 return 0;
849 }
850
851 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
852 struct mipi_dsi_device *device)
853 {
854 struct tegra_dsi *dsi = host_to_tegra(host);
855 int err;
856
857 dsi->flags = device->mode_flags;
858 dsi->format = device->format;
859 dsi->lanes = device->lanes;
860
861 if (dsi->master) {
862 err = tegra_dsi_ganged_setup(dsi->master, dsi);
863 if (err < 0) {
864 printk(BIOS_ERR, "failed to set up ganged mode: %d\n",
865 err);
866 return err;
867 }
868 }
869 return 0;
870 }
871
872 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
873 .attach = tegra_dsi_host_attach,
874 .transfer = tegra_dsi_host_transfer,
875 };
876
877 static int dsi_probe_if(int dsi_index,
878 struct soc_nvidia_tegra210_config *config)
879 {
880 struct tegra_dsi *dsi = &dsi_data[dsi_index];
881 int err;
882
883 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
884
885 /*
886 * Set default value. Will be taken from attached device once detected
887 */
888 dsi->flags = 0;
889 dsi->format = MIPI_DSI_FMT_RGB888;
890 dsi->lanes = 4;
891
892 /* get tegra_mipi_device */
893 dsi->mipi = tegra_mipi_request(&mipi_device_data[dsi_index], dsi_index);
894
895 /* calibrate */
896 err = tegra_dsi_pad_calibrate(dsi);
897 if (err < 0) {
898 printk(BIOS_ERR, "MIPI calibration failed: %d\n", err);
899 return err;
900 }
901
902 dsi->host.ops = &tegra_dsi_host_ops;
903 err = mipi_dsi_host_register(&dsi->host);
904 if (err < 0) {
905 printk(BIOS_ERR, "failed to register DSI host: %d\n", err);
906 return err;
907 }
908
909 /* get panel */
910 dsi->panel = panel_jdi_dsi_probe((struct mipi_dsi_device *)dsi->host.dev);
911 if (IS_ERR_PTR(dsi->panel)) {
912 printk(BIOS_ERR, "failed to get dsi panel\n");
913 return -EPTR;
914 }
915 dsi->panel->mode = config;
916 return 0;
917 }
918
919 static int dsi_probe(struct soc_nvidia_tegra210_config *config)
920 {
921 dsi_probe_if(DSI_A, config);
922 dsi_probe_if(DSI_B, config);
923 return 0;
924 }
925
926 static void tegra_dsi_init_regs(struct tegra_dsi *dsi)
927 {
928 int i;
929 for (i = 0; i < ARRAY_SIZE(init_reg); i++)
930 tegra_dsi_writel(dsi, 0, init_reg[i]);
931
932 if (dsi->slave)
933 tegra_dsi_init_regs(dsi->slave);
934 }
935
936 static int dsi_enable(struct soc_nvidia_tegra210_config *config)
937 {
938 struct tegra_dsi *dsi_a = &dsi_data[DSI_A];
939
940 dsi_probe(config);
941
942 /* set up clock and TimeOutRegisters */
943 tegra_output_dsi_setup_clock(dsi_a, config);
944
945 /* configure APB_MISC_GP_MIPI_PAD_CTRL_0 */
946 write32((unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0, DSIB_MODE_DSI);
947
948 /* configure phy interface timing registers */
949 tegra_dsi_set_phy_timing(dsi_a);
950
951 /* Initialize DSI registers */
952 tegra_dsi_init_regs(dsi_a);
953
954 /* prepare panel */
955 panel_jdi_prepare(dsi_a->panel);
956
957 /* enable dsi */
958 if (tegra_output_dsi_enable(dsi_a, config)) {
959 printk(BIOS_ERR,"%s: Error: failed to enable dsi output.\n",
960 __func__);
961 return -1;
962 }
963
964 return 0;
965 }
966
967 void dsi_display_startup(device_t dev)
968 {
969 struct soc_nvidia_tegra210_config *config = dev->chip_info;
970 struct display_controller *disp_ctrl =
971 (void *)config->display_controller;
972 u32 plld_rate;
973
974 u32 framebuffer_size_mb = config->framebuffer_size / MiB;
975 u32 framebuffer_base_mb= config->framebuffer_base / MiB;
976
977 printk(BIOS_INFO, "%s: entry: disp_ctrl: %p.\n",
978 __func__, disp_ctrl);
979
980 if (disp_ctrl == NULL) {
981 printk(BIOS_ERR, "Error: No dc is assigned by dt.\n");
982 return;
983 }
984
985 if (framebuffer_size_mb == 0){
986 framebuffer_size_mb = ALIGN_UP(config->display_xres *
987 config->display_yres *
988 (config->framebuffer_bits_per_pixel / 8), MiB)/MiB;
989 }
990
991 config->framebuffer_size = framebuffer_size_mb * MiB;
992 config->framebuffer_base = framebuffer_base_mb * MiB;
993
994 /*
995 * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
996 * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
997 * update_display_mode() for detail.
998 */
999 /* set default plld */
1000 plld_rate = clock_configure_plld(config->pixel_clock * 2);
1001 if (plld_rate == 0) {
1002 printk(BIOS_ERR, "dc: clock init failed\n");
1003 return;
1004 }
1005
1006 /* set disp1's clock source to PLLD_OUT0 */
1007 clock_configure_source(disp1, PLLD_OUT0, (plld_rate/KHz));
1008
1009 /* Init dc */
1010 if (tegra_dc_init(disp_ctrl)) {
1011 printk(BIOS_ERR, "dc: init failed\n");
1012 return;
1013 }
1014
1015 /* Configure dc mode */
1016 if (update_display_mode(disp_ctrl, config)) {
1017 printk(BIOS_ERR, "dc: failed to configure display mode.\n");
1018 return;
1019 }
1020
1021 /* Configure and enable dsi controller and panel */
1022 if (dsi_enable(config)) {
1023 printk(BIOS_ERR, "%s: failed to enable dsi controllers.\n",
1024 __func__);
1025 return;
1026 }
1027
1028 /* Set up window */
1029 update_window(config);
1030 printk(BIOS_INFO, "%s: display init done.\n", __func__);
1031
1032 /* Save panel information to cb tables */
1033 pass_mode_info_to_payload(config);
1034
1035 /*
1036 * After this point, it is payload's responsibility to allocate
1037 * framebuffer and sets the base address to dc's
1038 * WINBUF_START_ADDR register and enables window by setting dc's
1039 * DISP_DISP_WIN_OPTIONS register.
1040 */
1041 }
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