src/soc/nvidia/tegra132/sdram.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2014 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/io.h>
  17 #include <console/console.h>
  18 #include <delay.h>
  19 #include <soc/addressmap.h>
  20 #include <soc/clock.h>
  21 #include <soc/emc.h>
  22 #include <soc/mc.h>
  23 #include <soc/pmc.h>
  24 #include <soc/sdram.h>
  25 #include <stdlib.h>
  26
  27 static void sdram_patch(uintptr_t addr, uint32_t value)
  28 {
  29         if (addr)
  30                 write32((uint32_t *)addr, value);
  31 }
  32
  33 static void writebits(uint32_t value, uint32_t *addr, uint32_t mask)
  34 {
  35         clrsetbits_le32(addr, mask, (value & mask));
  36 }
  37
  38 /* PMC must be configured before clock-enable and de-reset of MC/EMC. */
  39 static void sdram_configure_pmc(const struct sdram_params *param,
  40                                 struct tegra_pmc_regs *regs)
  41 {
  42         /* VDDP Select */
  43         write32(&regs->vddp_sel, param->PmcVddpSel);
  44         udelay(param->PmcVddpSelWait);
  45
  46         /* Set DDR pad voltage */
  47         writebits(param->PmcDdrPwr, &regs->ddr_pwr, PMC_DDR_PWR_VAL_MASK);
  48
  49         /* Set package and DPD pad control */
  50         writebits(param->PmcDdrCfg, &regs->ddr_cfg,
  51                   (PMC_DDR_CFG_PKG_MASK | PMC_DDR_CFG_IF_MASK |
  52                    PMC_DDR_CFG_XM0_RESET_TRI_MASK |
  53                    PMC_DDR_CFG_XM0_RESET_DPDIO_MASK));
  54
  55         /* Turn on MEM IO Power */
  56         writebits(param->PmcNoIoPower, &regs->no_iopower,
  57                   (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK));
  58
  59         write32(&regs->reg_short, param->PmcRegShort);
  60 }
  61
  62 static void sdram_start_clocks(const struct sdram_params *param)
  63 {
  64         u32 is_same_freq = (param->McEmemArbMisc0 &
  65                             MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK) ? 1 : 0;
  66
  67         clock_sdram(param->PllMInputDivider, param->PllMFeedbackDivider,
  68                     param->PllMSelectDiv2, param->PllMSetupControl,
  69                     param->PllMPDLshiftPh45, param->PllMPDLshiftPh90,
  70                     param->PllMPDLshiftPh135, param->PllMKVCO,
  71                     param->PllMKCP, param->PllMStableTime,
  72                     param->EmcClockSource, is_same_freq);
  73 }
  74
  75 static void sdram_deassert_clock_enable_signal(const struct sdram_params *param,
  76                                                struct tegra_pmc_regs *regs)
  77 {
  78         clrbits_le32(&regs->por_dpd_ctrl,
  79                      PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK);
  80         udelay(param->PmcPorDpdCtrlWait);
  81 }
  82
  83 static void sdram_deassert_sel_dpd(const struct sdram_params *param,
  84                                    struct tegra_pmc_regs *regs)
  85 {
  86         clrbits_le32(&regs->por_dpd_ctrl,
  87                      (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK |
  88                       PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK));
  89         /*
  90          * Note NVIDIA recommended to always do 10us delay here and ignore
  91          * BCT.PmcPorDpdCtrlWait.
  92          * */
  93         udelay(10);
  94 }
  95
  96 static void sdram_set_swizzle(const struct sdram_params *param,
  97                               struct tegra_emc_regs *regs)
  98 {
  99         write32(&regs->swizzle_rank0_byte_cfg, param->EmcSwizzleRank0ByteCfg);
 100         write32(&regs->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0);
 101         write32(&regs->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1);
 102         write32(&regs->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2);
 103         write32(&regs->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3);
 104         write32(&regs->swizzle_rank1_byte_cfg, param->EmcSwizzleRank1ByteCfg);
 105         write32(&regs->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0);
 106         write32(&regs->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1);
 107         write32(&regs->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2);
 108         write32(&regs->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3);
 109 }
 110
 111 static void sdram_set_pad_controls(const struct sdram_params *param,
 112                                    struct tegra_emc_regs *regs)
 113 {
 114         /* Program the pad controls */
 115         write32(&regs->xm2cmdpadctrl, param->EmcXm2CmdPadCtrl);
 116         write32(&regs->xm2cmdpadctrl2, param->EmcXm2CmdPadCtrl2);
 117         write32(&regs->xm2cmdpadctrl3, param->EmcXm2CmdPadCtrl3);
 118         write32(&regs->xm2cmdpadctrl4, param->EmcXm2CmdPadCtrl4);
 119         write32(&regs->xm2cmdpadctrl5, param->EmcXm2CmdPadCtrl5);
 120
 121         write32(&regs->xm2dqspadctrl, param->EmcXm2DqsPadCtrl);
 122         write32(&regs->xm2dqspadctrl2, param->EmcXm2DqsPadCtrl2);
 123         write32(&regs->xm2dqspadctrl3, param->EmcXm2DqsPadCtrl3);
 124         write32(&regs->xm2dqspadctrl4, param->EmcXm2DqsPadCtrl4);
 125         write32(&regs->xm2dqspadctrl5, param->EmcXm2DqsPadCtrl5);
 126         write32(&regs->xm2dqspadctrl6, param->EmcXm2DqsPadCtrl6);
 127
 128         write32(&regs->xm2dqpadctrl, param->EmcXm2DqPadCtrl);
 129         write32(&regs->xm2dqpadctrl2, param->EmcXm2DqPadCtrl2);
 130         write32(&regs->xm2dqpadctrl3, param->EmcXm2DqPadCtrl3);
 131
 132         write32(&regs->xm2clkpadctrl, param->EmcXm2ClkPadCtrl);
 133         write32(&regs->xm2clkpadctrl2, param->EmcXm2ClkPadCtrl2);
 134
 135         write32(&regs->xm2comppadctrl, param->EmcXm2CompPadCtrl);
 136
 137         write32(&regs->xm2vttgenpadctrl, param->EmcXm2VttGenPadCtrl);
 138         write32(&regs->xm2vttgenpadctrl2, param->EmcXm2VttGenPadCtrl2);
 139         write32(&regs->xm2vttgenpadctrl3, param->EmcXm2VttGenPadCtrl3);
 140
 141         write32(&regs->ctt_term_ctrl, param->EmcCttTermCtrl);
 142 }
 143
 144 static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs)
 145 {
 146         write32(&regs->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE);
 147 }
 148
 149 static void sdram_init_mc(const struct sdram_params *param,
 150                           struct tegra_mc_regs *regs)
 151 {
 152         /* Initialize MC VPR settings */
 153         write32(&regs->display_snap_ring, param->McDisplaySnapRing);
 154         write32(&regs->video_protect_bom, param->McVideoProtectBom);
 155         write32(&regs->video_protect_bom_adr_hi,
 156                 param->McVideoProtectBomAdrHi);
 157         write32(&regs->video_protect_size_mb, param->McVideoProtectSizeMb);
 158         write32(&regs->video_protect_vpr_override,
 159                 param->McVideoProtectVprOverride);
 160         write32(&regs->video_protect_vpr_override1,
 161                 param->McVideoProtectVprOverride1);
 162         write32(&regs->video_protect_gpu_override_0,
 163                 param->McVideoProtectGpuOverride0);
 164         write32(&regs->video_protect_gpu_override_1,
 165                 param->McVideoProtectGpuOverride1);
 166
 167         /* Program SDRAM geometry paarameters */
 168         write32(&regs->emem_adr_cfg, param->McEmemAdrCfg);
 169         write32(&regs->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0);
 170         write32(&regs->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1);
 171
 172         /* Program bank swizzling */
 173         write32(&regs->emem_bank_swizzle_cfg0, param->McEmemAdrCfgBankMask0);
 174         write32(&regs->emem_bank_swizzle_cfg1, param->McEmemAdrCfgBankMask1);
 175         write32(&regs->emem_bank_swizzle_cfg2, param->McEmemAdrCfgBankMask2);
 176         write32(&regs->emem_bank_swizzle_cfg3,
 177                 param->McEmemAdrCfgBankSwizzle3);
 178
 179         /* Program external memory aperature (base and size) */
 180         write32(&regs->emem_cfg, param->McEmemCfg);
 181
 182         /* Program SEC carveout (base and size) */
 183         write32(&regs->sec_carveout_bom, param->McSecCarveoutBom);
 184         write32(&regs->sec_carveout_adr_hi, param->McSecCarveoutAdrHi);
 185         write32(&regs->sec_carveout_size_mb, param->McSecCarveoutSizeMb);
 186
 187         /* Program MTS carveout (base and size) */
 188         write32(&regs->mts_carveout_bom, param->McMtsCarveoutBom);
 189         write32(&regs->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi);
 190         write32(&regs->mts_carveout_size_mb, param->McMtsCarveoutSizeMb);
 191
 192         /* Program the memory arbiter */
 193         write32(&regs->emem_arb_cfg, param->McEmemArbCfg);
 194         write32(&regs->emem_arb_outstanding_req,
 195                 param->McEmemArbOutstandingReq);
 196         write32(&regs->emem_arb_timing_rcd, param->McEmemArbTimingRcd);
 197         write32(&regs->emem_arb_timing_rp, param->McEmemArbTimingRp);
 198         write32(&regs->emem_arb_timing_rc, param->McEmemArbTimingRc);
 199         write32(&regs->emem_arb_timing_ras, param->McEmemArbTimingRas);
 200         write32(&regs->emem_arb_timing_faw, param->McEmemArbTimingFaw);
 201         write32(&regs->emem_arb_timing_rrd, param->McEmemArbTimingRrd);
 202         write32(&regs->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre);
 203         write32(&regs->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre);
 204         write32(&regs->emem_arb_timing_r2r, param->McEmemArbTimingR2R);
 205         write32(&regs->emem_arb_timing_w2w, param->McEmemArbTimingW2W);
 206         write32(&regs->emem_arb_timing_r2w, param->McEmemArbTimingR2W);
 207         write32(&regs->emem_arb_timing_w2r, param->McEmemArbTimingW2R);
 208         write32(&regs->emem_arb_da_turns, param->McEmemArbDaTurns);
 209         write32(&regs->emem_arb_da_covers, param->McEmemArbDaCovers);
 210         write32(&regs->emem_arb_misc0, param->McEmemArbMisc0);
 211         write32(&regs->emem_arb_misc1, param->McEmemArbMisc1);
 212         write32(&regs->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle);
 213         write32(&regs->emem_arb_override, param->McEmemArbOverride);
 214         write32(&regs->emem_arb_override_1, param->McEmemArbOverride1);
 215         write32(&regs->emem_arb_rsv, param->McEmemArbRsv);
 216
 217         /* Program extra snap levels for display client */
 218         write32(&regs->dis_extra_snap_levels, param->McDisExtraSnapLevels);
 219
 220         /* Trigger MC timing update */
 221         write32(&regs->timing_control, MC_TIMING_CONTROL_TIMING_UPDATE);
 222
 223         /* Program second-level clock enable overrides */
 224         write32(&regs->clken_override, param->McClkenOverride);
 225
 226         /* Program statistics gathering */
 227         write32(&regs->stat_control, param->McStatControl);
 228 }
 229
 230 static void sdram_init_emc(const struct sdram_params *param,
 231                            struct tegra_emc_regs *regs)
 232 {
 233         /* Program SDRAM geometry parameters */
 234         write32(&regs->adr_cfg, param->EmcAdrCfg);
 235
 236         /* Program second-level clock enable overrides */
 237         write32(&regs->clken_override, param->EmcClkenOverride);
 238
 239         /* Program EMC pad auto calibration */
 240         write32(&regs->auto_cal_interval, param->EmcAutoCalInterval);
 241         write32(&regs->auto_cal_config2, param->EmcAutoCalConfig2);
 242         write32(&regs->auto_cal_config3, param->EmcAutoCalConfig3);
 243         write32(&regs->auto_cal_config, param->EmcAutoCalConfig);
 244         udelay(param->EmcAutoCalWait);
 245 }
 246
 247 static void sdram_set_emc_timing(const struct sdram_params *param,
 248                                  struct tegra_emc_regs *regs)
 249 {
 250         /* Program EMC timing configuration */
 251         write32(&regs->cfg_2, param->EmcCfg2);
 252         write32(&regs->cfg_pipe, param->EmcCfgPipe);
 253         write32(&regs->dbg, param->EmcDbg);
 254         write32(&regs->cmdq, param->EmcCmdQ);
 255         write32(&regs->mc2emcq, param->EmcMc2EmcQ);
 256         write32(&regs->mrs_wait_cnt, param->EmcMrsWaitCnt);
 257         write32(&regs->mrs_wait_cnt2, param->EmcMrsWaitCnt2);
 258         write32(&regs->fbio_cfg5, param->EmcFbioCfg5);
 259         write32(&regs->rc, param->EmcRc);
 260         write32(&regs->rfc, param->EmcRfc);
 261         write32(&regs->rfc_slr, param->EmcRfcSlr);
 262         write32(&regs->ras, param->EmcRas);
 263         write32(&regs->rp, param->EmcRp);
 264         write32(&regs->r2r, param->EmcR2r);
 265         write32(&regs->w2w, param->EmcW2w);
 266         write32(&regs->r2w, param->EmcR2w);
 267         write32(&regs->w2r, param->EmcW2r);
 268         write32(&regs->r2p, param->EmcR2p);
 269         write32(&regs->w2p, param->EmcW2p);
 270         write32(&regs->rd_rcd, param->EmcRdRcd);
 271         write32(&regs->wr_rcd, param->EmcWrRcd);
 272         write32(&regs->rrd, param->EmcRrd);
 273         write32(&regs->rext, param->EmcRext);
 274         write32(&regs->wext, param->EmcWext);
 275         write32(&regs->wdv, param->EmcWdv);
 276         write32(&regs->wdv_mask, param->EmcWdvMask);
 277         write32(&regs->quse, param->EmcQUse);
 278         write32(&regs->quse_width, param->EmcQuseWidth);
 279         write32(&regs->ibdly, param->EmcIbdly);
 280         write32(&regs->einput, param->EmcEInput);
 281         write32(&regs->einput_duration, param->EmcEInputDuration);
 282         write32(&regs->puterm_extra, param->EmcPutermExtra);
 283         write32(&regs->puterm_width, param->EmcPutermWidth);
 284         write32(&regs->puterm_adj, param->EmcPutermAdj);
 285         write32(&regs->cdb_cntl_1, param->EmcCdbCntl1);
 286         write32(&regs->cdb_cntl_2, param->EmcCdbCntl2);
 287         write32(&regs->cdb_cntl_3, param->EmcCdbCntl3);
 288         write32(&regs->qrst, param->EmcQRst);
 289         write32(&regs->qsafe, param->EmcQSafe);
 290         write32(&regs->rdv, param->EmcRdv);
 291         write32(&regs->rdv_mask, param->EmcRdvMask);
 292         write32(&regs->qpop, param->EmcQpop);
 293         write32(&regs->ctt, param->EmcCtt);
 294         write32(&regs->ctt_duration, param->EmcCttDuration);
 295         write32(&regs->refresh, param->EmcRefresh);
 296         write32(&regs->burst_refresh_num, param->EmcBurstRefreshNum);
 297         write32(&regs->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt);
 298         write32(&regs->pdex2wr, param->EmcPdEx2Wr);
 299         write32(&regs->pdex2rd, param->EmcPdEx2Rd);
 300         write32(&regs->pchg2pden, param->EmcPChg2Pden);
 301         write32(&regs->act2pden, param->EmcAct2Pden);
 302         write32(&regs->ar2pden, param->EmcAr2Pden);
 303         write32(&regs->rw2pden, param->EmcRw2Pden);
 304         write32(&regs->txsr, param->EmcTxsr);
 305         write32(&regs->txsrdll, param->EmcTxsrDll);
 306         write32(&regs->tcke, param->EmcTcke);
 307         write32(&regs->tckesr, param->EmcTckesr);
 308         write32(&regs->tpd, param->EmcTpd);
 309         write32(&regs->tfaw, param->EmcTfaw);
 310         write32(&regs->trpab, param->EmcTrpab);
 311         write32(&regs->tclkstable, param->EmcTClkStable);
 312         write32(&regs->tclkstop, param->EmcTClkStop);
 313         write32(&regs->trefbw, param->EmcTRefBw);
 314         write32(&regs->odt_write, param->EmcOdtWrite);
 315         write32(&regs->odt_read, param->EmcOdtRead);
 316         write32(&regs->fbio_cfg6, param->EmcFbioCfg6);
 317         write32(&regs->cfg_dig_dll, param->EmcCfgDigDll);
 318         write32(&regs->cfg_dig_dll_period, param->EmcCfgDigDllPeriod);
 319
 320         /* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */
 321         write32(&regs->fbio_spare, param->EmcFbioSpare & 0xfffffffd);
 322
 323         write32(&regs->cfg_rsv, param->EmcCfgRsv);
 324         write32(&regs->dll_xform_dqs0, param->EmcDllXformDqs0);
 325         write32(&regs->dll_xform_dqs1, param->EmcDllXformDqs1);
 326         write32(&regs->dll_xform_dqs2, param->EmcDllXformDqs2);
 327         write32(&regs->dll_xform_dqs3, param->EmcDllXformDqs3);
 328         write32(&regs->dll_xform_dqs4, param->EmcDllXformDqs4);
 329         write32(&regs->dll_xform_dqs5, param->EmcDllXformDqs5);
 330         write32(&regs->dll_xform_dqs6, param->EmcDllXformDqs6);
 331         write32(&regs->dll_xform_dqs7, param->EmcDllXformDqs7);
 332         write32(&regs->dll_xform_dqs8, param->EmcDllXformDqs8);
 333         write32(&regs->dll_xform_dqs9, param->EmcDllXformDqs9);
 334         write32(&regs->dll_xform_dqs10, param->EmcDllXformDqs10);
 335         write32(&regs->dll_xform_dqs11, param->EmcDllXformDqs11);
 336         write32(&regs->dll_xform_dqs12, param->EmcDllXformDqs12);
 337         write32(&regs->dll_xform_dqs13, param->EmcDllXformDqs13);
 338         write32(&regs->dll_xform_dqs14, param->EmcDllXformDqs14);
 339         write32(&regs->dll_xform_dqs15, param->EmcDllXformDqs15);
 340         write32(&regs->dll_xform_quse0, param->EmcDllXformQUse0);
 341         write32(&regs->dll_xform_quse1, param->EmcDllXformQUse1);
 342         write32(&regs->dll_xform_quse2, param->EmcDllXformQUse2);
 343         write32(&regs->dll_xform_quse3, param->EmcDllXformQUse3);
 344         write32(&regs->dll_xform_quse4, param->EmcDllXformQUse4);
 345         write32(&regs->dll_xform_quse5, param->EmcDllXformQUse5);
 346         write32(&regs->dll_xform_quse6, param->EmcDllXformQUse6);
 347         write32(&regs->dll_xform_quse7, param->EmcDllXformQUse7);
 348         write32(&regs->dll_xform_quse8, param->EmcDllXformQUse8);
 349         write32(&regs->dll_xform_quse9, param->EmcDllXformQUse9);
 350         write32(&regs->dll_xform_quse10, param->EmcDllXformQUse10);
 351         write32(&regs->dll_xform_quse11, param->EmcDllXformQUse11);
 352         write32(&regs->dll_xform_quse12, param->EmcDllXformQUse12);
 353         write32(&regs->dll_xform_quse13, param->EmcDllXformQUse13);
 354         write32(&regs->dll_xform_quse14, param->EmcDllXformQUse14);
 355         write32(&regs->dll_xform_quse15, param->EmcDllXformQUse15);
 356         write32(&regs->dll_xform_dq0, param->EmcDllXformDq0);
 357         write32(&regs->dll_xform_dq1, param->EmcDllXformDq1);
 358         write32(&regs->dll_xform_dq2, param->EmcDllXformDq2);
 359         write32(&regs->dll_xform_dq3, param->EmcDllXformDq3);
 360         write32(&regs->dll_xform_dq4, param->EmcDllXformDq4);
 361         write32(&regs->dll_xform_dq5, param->EmcDllXformDq5);
 362         write32(&regs->dll_xform_dq6, param->EmcDllXformDq6);
 363         write32(&regs->dll_xform_dq7, param->EmcDllXformDq7);
 364         write32(&regs->dll_xform_addr0, param->EmcDllXformAddr0);
 365         write32(&regs->dll_xform_addr1, param->EmcDllXformAddr1);
 366         write32(&regs->dll_xform_addr2, param->EmcDllXformAddr2);
 367         write32(&regs->dll_xform_addr3, param->EmcDllXformAddr3);
 368         write32(&regs->dll_xform_addr4, param->EmcDllXformAddr4);
 369         write32(&regs->dll_xform_addr5, param->EmcDllXformAddr5);
 370         write32(&regs->acpd_control, param->EmcAcpdControl);
 371         write32(&regs->dsr_vttgen_drv, param->EmcDsrVttgenDrv);
 372         write32(&regs->txdsrvttgen, param->EmcTxdsrvttgen);
 373         write32(&regs->bgbias_ctl0, param->EmcBgbiasCtl0);
 374
 375         /*
 376          * Set pipe bypass enable bits before sending any DRAM commands.
 377          * Note other bits in EMC_CFG must be set AFTER REFCTRL is configured.
 378          */
 379         writebits(param->EmcCfg, &regs->cfg,
 380                   (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK |
 381                    EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK |
 382                    EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK));
 383 }
 384
 385 static void sdram_patch_bootrom(const struct sdram_params *param,
 386                                 struct tegra_mc_regs *regs)
 387 {
 388         if (param->BootRomPatchControl & BOOT_ROM_PATCH_CONTROL_ENABLE_MASK) {
 389                 uintptr_t addr = ((param->BootRomPatchControl &
 390                                   BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >>
 391                                   BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT);
 392                 addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2);
 393                 write32((uint32_t *)addr, param->BootRomPatchData);
 394                 write32(&regs->timing_control, 1);
 395         }
 396 }
 397
 398 static void sdram_set_dpd3(const struct sdram_params *param,
 399                            struct tegra_pmc_regs *regs)
 400 {
 401         /* Program DPD request */
 402         write32(&regs->io_dpd3_req, param->PmcIoDpd3Req);
 403         udelay(param->PmcIoDpd3ReqWait);
 404 }
 405
 406 static void sdram_set_dli_trims(const struct sdram_params *param,
 407                                 struct tegra_emc_regs *regs)
 408 {
 409         /* Program DLI trims */
 410         write32(&regs->dli_trim_txdqs0, param->EmcDliTrimTxDqs0);
 411         write32(&regs->dli_trim_txdqs1, param->EmcDliTrimTxDqs1);
 412         write32(&regs->dli_trim_txdqs2, param->EmcDliTrimTxDqs2);
 413         write32(&regs->dli_trim_txdqs3, param->EmcDliTrimTxDqs3);
 414         write32(&regs->dli_trim_txdqs4, param->EmcDliTrimTxDqs4);
 415         write32(&regs->dli_trim_txdqs5, param->EmcDliTrimTxDqs5);
 416         write32(&regs->dli_trim_txdqs6, param->EmcDliTrimTxDqs6);
 417         write32(&regs->dli_trim_txdqs7, param->EmcDliTrimTxDqs7);
 418         write32(&regs->dli_trim_txdqs8, param->EmcDliTrimTxDqs8);
 419         write32(&regs->dli_trim_txdqs9, param->EmcDliTrimTxDqs9);
 420         write32(&regs->dli_trim_txdqs10, param->EmcDliTrimTxDqs10);
 421         write32(&regs->dli_trim_txdqs11, param->EmcDliTrimTxDqs11);
 422         write32(&regs->dli_trim_txdqs12, param->EmcDliTrimTxDqs12);
 423         write32(&regs->dli_trim_txdqs13, param->EmcDliTrimTxDqs13);
 424         write32(&regs->dli_trim_txdqs14, param->EmcDliTrimTxDqs14);
 425         write32(&regs->dli_trim_txdqs15, param->EmcDliTrimTxDqs15);
 426
 427         write32(&regs->ca_training_timing_cntl1,
 428                 param->EmcCaTrainingTimingCntl1);
 429         write32(&regs->ca_training_timing_cntl2,
 430                 param->EmcCaTrainingTimingCntl2);
 431
 432         sdram_trigger_emc_timing_update(regs);
 433         udelay(param->EmcTimingControlWait);
 434 }
 435
 436 static void sdram_set_clock_enable_signal(const struct sdram_params *param,
 437                                           struct tegra_emc_regs *regs)
 438 {
 439         volatile uint32_t dummy = 0;
 440         clrbits_le32(&regs->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK |
 441                                   EMC_PIN_CKE_MASK));
 442         /*
 443          * Assert dummy read of PIN register to ensure above write to PIN
 444          * register went through. 200 is the recommended value by NVIDIA.
 445          */
 446         dummy |= read32(&regs->pin);
 447         udelay(200 + param->EmcPinExtraWait);
 448
 449         /* Deassert reset */
 450         setbits_le32(&regs->pin, EMC_PIN_RESET_INACTIVE);
 451         /*
 452          * Assert dummy read of PIN register to ensure above write to PIN
 453          * register went through. 200 is the recommended value by NVIDIA.
 454          */
 455         dummy |= read32(&regs->pin);
 456         udelay(500 + param->EmcPinExtraWait);
 457
 458         /* Enable clock enable signal */
 459         setbits_le32(&regs->pin, EMC_PIN_CKE_NORMAL);
 460         /*
 461          * Assert dummy read of PIN register to ensure above write to PIN
 462          * register went through. 200 is the recommended value by NVIDIA.
 463          */
 464         dummy |= read32(&regs->pin);
 465         udelay(param->EmcPinProgramWait);
 466
 467         if (!dummy) {
 468                 die("Failed to program EMC pin.");
 469         }
 470
 471         /* Send NOP (trigger) */
 472         writebits(((1 << EMC_NOP_NOP_CMD_SHIFT) |
 473                    (param->EmcDevSelect << EMC_NOP_NOP_DEV_SELECTN_SHIFT)),
 474                   &regs->nop,
 475                   EMC_NOP_NOP_CMD_MASK | EMC_NOP_NOP_DEV_SELECTN_MASK);
 476 }
 477
 478 static void sdram_init_ddr3(const struct sdram_params *param, struct tegra_emc_regs *regs)
 479 {
 480         /* Write mode registers */
 481         write32(&regs->emrs2, param->EmcEmrs2);
 482         write32(&regs->emrs3, param->EmcEmrs3);
 483         write32(&regs->emrs, param->EmcEmrs);
 484         write32(&regs->mrs, param->EmcMrs);
 485
 486         if (param->EmcExtraModeRegWriteEnable) {
 487                 write32(&regs->mrs, param->EmcMrsExtra);
 488         }
 489
 490         write32(&regs->zq_cal, param->EmcZcalInitDev0);
 491         udelay(param->EmcZcalInitWait);
 492
 493         if ((param->EmcDevSelect & 2) == 0) {
 494                 write32(&regs->zq_cal, param->EmcZcalInitDev1);
 495                 udelay(param->EmcZcalInitWait);
 496         }
 497 }
 498
 499 static void sdram_init_lpddr3(const struct sdram_params *param, struct tegra_emc_regs *regs)
 500 {
 501         /* Precharge all banks. DEV_SELECTN = 0 => Select all devices */
 502         write32(&regs->pre,
 503                 ((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1));
 504
 505         /* Send Reset MRW command */
 506         write32(&regs->mrw, param->EmcMrwResetCommand);
 507         udelay(param->EmcMrwResetNInitWait);
 508
 509         write32(&regs->mrw, param->EmcZcalInitDev0);
 510         udelay(param->EmcZcalInitWait);
 511
 512         if ((param->EmcDevSelect & 2) == 0)
 513         {
 514                 write32(&regs->mrw, param->EmcZcalInitDev1);
 515                 udelay(param->EmcZcalInitWait);
 516         }
 517
 518         /* Write mode registers */
 519         write32(&regs->mrw2, param->EmcMrw2);
 520         write32(&regs->mrw, param->EmcMrw1);
 521         write32(&regs->mrw3, param->EmcMrw3);
 522         write32(&regs->mrw4, param->EmcMrw4);
 523
 524         if (param->EmcExtraModeRegWriteEnable) {
 525                 write32(&regs->mrw, param->EmcMrwExtra);
 526         }
 527 }
 528
 529 static void sdram_init_zq_calibration(const struct sdram_params *param,
 530                                       struct tegra_emc_regs *regs)
 531 {
 532         if ((param->EmcZcalWarmColdBootEnables &
 533              EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK) == 1) {
 534                 /* Need to initialize ZCAL on coldboot. */
 535                 if (param->MemoryType == NvBootMemoryType_Ddr3)
 536                         sdram_init_ddr3(param, regs);
 537                 else if (param->MemoryType == NvBootMemoryType_LpDdr2)
 538                         sdram_init_lpddr3(param, regs);
 539         } else {
 540                 /* Wait for DLL stablization time even without ZCAL */
 541                 udelay(param->EmcZcalInitWait);
 542         }
 543 }
 544
 545 static void sdram_set_zq_calibration(const struct sdram_params *param,
 546                                      struct tegra_emc_regs *regs)
 547 {
 548         /* Start periodic ZQ calibration */
 549         write32(&regs->zcal_interval, param->EmcZcalInterval);
 550         write32(&regs->zcal_wait_cnt, param->EmcZcalWaitCnt);
 551         write32(&regs->zcal_mrw_cmd, param->EmcZcalMrwCmd);
 552 }
 553
 554 static void sdram_set_refresh(const struct sdram_params *param,
 555                               struct tegra_emc_regs *regs)
 556 {
 557         /* Insert burst refresh */
 558         if (param->EmcExtraRefreshNum > 0) {
 559                 uint32_t refresh_num = (1 << param->EmcExtraRefreshNum) - 1;
 560                 writebits((EMC_REF_CMD_REFRESH | EMC_REF_NORMAL_ENABLED |
 561                            (refresh_num << EMC_REF_NUM_SHIFT) |
 562                            (param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT)),
 563                           &regs->ref, (EMC_REF_CMD_MASK | EMC_REF_NORMAL_MASK |
 564                                        EMC_REF_NUM_MASK |
 565                                        EMC_REF_DEV_SELECTN_MASK));
 566         }
 567
 568         /* Enable refresh */
 569         write32(&regs->refctrl,
 570                 (param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED));
 571
 572         write32(&regs->dyn_self_ref_control, param->EmcDynSelfRefControl);
 573         write32(&regs->cfg, param->EmcCfg);
 574         write32(&regs->sel_dpd_ctrl, param->EmcSelDpdCtrl);
 575
 576         /* Write addr swizzle lock bit */
 577         write32(&regs->fbio_spare, param->EmcFbioSpare);
 578
 579         /* Re-trigger timing to latch power saving functions */
 580         sdram_trigger_emc_timing_update(regs);
 581 }
 582
 583 static void sdram_enable_arbiter(const struct sdram_params *param)
 584 {
 585         /* TODO(hungte) Move values here to standalone header file. */
 586         uint32_t *AHB_ARBITRATION_XBAR_CTRL = (uint32_t*)(0x6000c000 + 0xe0);
 587         setbits_le32(AHB_ARBITRATION_XBAR_CTRL,
 588                      param->AhbArbitrationXbarCtrlMemInitDone << 16);
 589 }
 590
 591 static void sdram_lock_carveouts(const struct sdram_params *param,
 592                                  struct tegra_mc_regs *regs)
 593 {
 594         /* Lock carveouts, and emem_cfg registers */
 595         write32(&regs->video_protect_reg_ctrl,
 596                 param->McVideoProtectWriteAccess);
 597         write32(&regs->emem_cfg_access_ctrl,
 598                 MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED);
 599         write32(&regs->sec_carveout_reg_ctrl,
 600                 param->McSecCarveoutProtectWriteAccess);
 601         write32(&regs->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl);
 602 }
 603
 604 void sdram_init(const struct sdram_params *param)
 605 {
 606         struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE;
 607         struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE;
 608         struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE;
 609
 610         printk(BIOS_DEBUG, "Initializing SDRAM of type %d with %dKHz\n",
 611                 param->MemoryType, clock_get_pll_input_khz() *
 612                 param->PllMFeedbackDivider / param->PllMInputDivider /
 613                 (1 + param->PllMSelectDiv2));
 614         if (param->MemoryType != NvBootMemoryType_Ddr3 &&
 615             param->MemoryType != NvBootMemoryType_LpDdr2)
 616                 die("Unsupported memory type!\n");
 617
 618         sdram_configure_pmc(param, pmc);
 619         sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1);
 620
 621         sdram_start_clocks(param);
 622         sdram_patch(param->EmcBctSpare2, param->EmcBctSpare3);
 623
 624         sdram_deassert_sel_dpd(param, pmc);
 625         sdram_set_swizzle(param, emc);
 626         sdram_set_pad_controls(param, emc);
 627         sdram_patch(param->EmcBctSpare4, param->EmcBctSpare5);
 628
 629         sdram_trigger_emc_timing_update(emc);
 630         sdram_init_mc(param, mc);
 631         sdram_init_emc(param, emc);
 632         sdram_patch(param->EmcBctSpare6, param->EmcBctSpare7);
 633
 634         sdram_set_emc_timing(param, emc);
 635         sdram_patch_bootrom(param, mc);
 636         sdram_set_dpd3(param, pmc);
 637         sdram_set_dli_trims(param, emc);
 638         sdram_deassert_clock_enable_signal(param, pmc);
 639         sdram_set_clock_enable_signal(param, emc);
 640         sdram_init_zq_calibration(param, emc);
 641         sdram_patch(param->EmcBctSpare8, param->EmcBctSpare9);
 642
 643         sdram_set_zq_calibration(param, emc);
 644         sdram_patch(param->EmcBctSpare10, param->EmcBctSpare11);
 645
 646         sdram_trigger_emc_timing_update(emc);
 647         sdram_set_refresh(param, emc);
 648         sdram_enable_arbiter(param);
 649         sdram_lock_carveouts(param, mc);
 650
 651         sdram_lp0_save_params(param);
 652 }
 653
 654 uint32_t sdram_get_ram_code(void)
 655 {
 656         struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE;
 657         return ((read32(&pmc->strapping_opt_a) &
 658                  PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >>
 659                 PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT);
 660 }