2 * This file is part of the coreboot project.
4 * Copyright 2014 Google Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <console/console.h>
21 #include <soc/addressmap.h>
22 #include <soc/clock.h>
23 #include <device/device.h>
24 #include <soc/nvidia/tegra/types.h>
25 #include <soc/display.h>
26 #include <soc/mipi_dsi.h>
27 #include <soc/mipi_display.h>
28 #include <soc/tegra_dsi.h>
29 #include <soc/mipi-phy.h>
31 int mipi_dphy_set_timing(struct tegra_dsi
*dsi
)
34 u32 freq
= (dsi
->clk_rate
* 2) / 1000000;
36 u32 thsdexit
= (DSI_PHY_TIMING_DIV(120, (freq
)));
37 u32 thstrial
= (((3) + (DSI_PHY_TIMING_DIV((DSI_THSTRAIL_VAL(freq
)),
39 u32 tdatzero
= DSI_PHY_TIMING_DIV(((145) + (5 * (DSI_TBIT(freq
)))),
41 u32 thsprepare
= DSI_PHY_TIMING_DIV((65 + (5*(DSI_TBIT(freq
)))), freq
);
42 u32 tclktrial
= (DSI_PHY_TIMING_DIV(80, freq
));
43 u32 tclkpost
= ((DSI_PHY_TIMING_DIV(((70) + ((52) * (DSI_TBIT(freq
)))),
45 u32 tclkzero
= (DSI_PHY_TIMING_DIV(260, freq
));
46 u32 ttlpx
= (DSI_PHY_TIMING_DIV(60, freq
)) ;
47 u32 tclkprepare
= (DSI_PHY_TIMING_DIV(60, freq
));
48 u32 tclkpre
= 1; //min = 8*UI per mipi spec, tclk_pre=0 should be ok, but using 1 value
49 u32 twakeup
= 0x7F; //min = 1ms
66 value
= (thsdexit
<< 24) |
70 tegra_dsi_writel(dsi
, value
, DSI_PHY_TIMING_0
);
72 value
= (tclktrial
<< 24) |
76 tegra_dsi_writel(dsi
, value
, DSI_PHY_TIMING_1
);
78 value
= (tclkprepare
<< 16) |
81 tegra_dsi_writel(dsi
, value
, DSI_PHY_TIMING_2
);
83 value
= (ttaget
<< 16) |
86 tegra_dsi_writel(dsi
, value
, DSI_BTA_TIMING
);