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tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / soc / nvidia / tegra132 / dsi.c
blobf2a2b3c83c2d679911b47adad4228b977634d61d
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <console/console.h>
16 #include <arch/io.h>
17 #include <stdint.h>
18 #include <lib.h>
19 #include <stdlib.h>
20 #include <delay.h>
21 #include <timer.h>
22 #include <soc/addressmap.h>
23 #include <soc/clock.h>
24 #include <device/device.h>
25 #include <edid.h>
26 #include <soc/nvidia/tegra/types.h>
27 #include <soc/nvidia/tegra/dc.h>
28 #include "chip.h"
29 #include <soc/display.h>
30 #include <soc/mipi_dsi.h>
31 #include <soc/mipi_display.h>
32 #include <soc/tegra_dsi.h>
33 #include <soc/mipi-phy.h>
34 #include "jdi_25x18_display/panel-jdi-lpm102a188a.h"
35
36 struct tegra_mipi_device mipi_device_data[NUM_DSI];
37
38 struct tegra_dsi dsi_data[NUM_DSI] = {
39 {
40 .regs = (void *)TEGRA_DSIA_BASE,
41 .channel = 0,
42 .slave = &dsi_data[DSI_B],
43 .master = NULL,
44 .video_fifo_depth = MAX_DSI_VIDEO_FIFO_DEPTH,
45 .host_fifo_depth = MAX_DSI_HOST_FIFO_DEPTH,
46 },
47 {
48 .regs = (void *)TEGRA_DSIB_BASE,
49 .channel = 0,
50 .slave = NULL,
51 .master = &dsi_data[DSI_A],
52 .video_fifo_depth = MAX_DSI_VIDEO_FIFO_DEPTH,
53 .host_fifo_depth = MAX_DSI_HOST_FIFO_DEPTH,
54 },
55 };
56
57 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
58 {
59 return container_of(host, struct tegra_dsi, host);
60 }
61
62 /*
63 * non-burst mode with sync pulses
64 */
65 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
66 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
67 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
68 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
69 PKT_LP,
70 [ 1] = 0,
71 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
72 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
73 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
74 PKT_LP,
75 [ 3] = 0,
76 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
77 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
78 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
79 PKT_LP,
80 [ 5] = 0,
81 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
82 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
83 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
84 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
85 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
86 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
87 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
88 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
89 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
90 PKT_LP,
91 [ 9] = 0,
92 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
93 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
94 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
95 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
96 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
97 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
98 };
99
100 /*
101 * non-burst mode with sync events
102 */
103 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
104 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
105 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
106 PKT_LP,
107 [ 1] = 0,
108 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
109 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
110 PKT_LP,
111 [ 3] = 0,
112 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
113 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
114 PKT_LP,
115 [ 5] = 0,
116
117 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
118 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
119 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
120
121 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
122 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
123 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
124 PKT_LP,
125 [ 9] = 0,
126
127 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
128 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
129 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
130
131 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
132 };
133
134 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
135 [ 0] = 0,
136 [ 1] = 0,
137 [ 2] = 0,
138 [ 3] = 0,
139 [ 4] = 0,
140 [ 5] = 0,
141 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
142 [ 7] = 0,
143 [ 8] = 0,
144 [ 9] = 0,
145 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
146 [11] = 0,
147 };
148
149 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
150 {
151 int err;
152
153 err = mipi_dphy_set_timing(dsi);
154 if (err < 0) {
155 printk(BIOS_ERR, "failed to set D-PHY timing: %d\n", err);
156 return err;
157 }
158
159 if (dsi->slave)
160 tegra_dsi_set_phy_timing(dsi->slave);
161 return 0;
162 }
163
164 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
165 unsigned int *mulp, unsigned int *divp)
166 {
167 switch (format) {
168 case MIPI_DSI_FMT_RGB666_PACKED:
169 case MIPI_DSI_FMT_RGB888:
170 *mulp = 3;
171 *divp = 1;
172 break;
173
174 case MIPI_DSI_FMT_RGB565:
175 *mulp = 2;
176 *divp = 1;
177 break;
178
179 case MIPI_DSI_FMT_RGB666:
180 *mulp = 9;
181 *divp = 4;
182 break;
183
184 default:
185 return -EINVAL;
186 }
187 return 0;
188 }
189
190 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
191 enum tegra_dsi_format *fmt)
192 {
193 switch (format) {
194 case MIPI_DSI_FMT_RGB888:
195 *fmt = TEGRA_DSI_FORMAT_24P;
196 break;
197
198 case MIPI_DSI_FMT_RGB666:
199 *fmt = TEGRA_DSI_FORMAT_18NP;
200 break;
201
202 case MIPI_DSI_FMT_RGB666_PACKED:
203 *fmt = TEGRA_DSI_FORMAT_18P;
204 break;
205
206 case MIPI_DSI_FMT_RGB565:
207 *fmt = TEGRA_DSI_FORMAT_16P;
208 break;
209
210 default:
211 return -EINVAL;
212 }
213 return 0;
214 }
215
216 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
217 unsigned int size)
218 {
219 u32 value;
220
221 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
222 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
223
224 value = DSI_GANGED_MODE_CONTROL_ENABLE;
225 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
226 }
227
228 static void tegra_dsi_enable(struct tegra_dsi *dsi)
229 {
230 u32 value;
231
232 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
233 value |= DSI_POWER_CONTROL_ENABLE;
234 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
235
236 if (dsi->slave)
237 tegra_dsi_enable(dsi->slave);
238 }
239
240 static int tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
241 const struct soc_nvidia_tegra132_config *mode)
242 {
243 unsigned int hact, hsw, hbp, hfp, i, mul, div;
244 enum tegra_dsi_format format;
245 const u32 *pkt_seq;
246 u32 value;
247 int err;
248
249 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
250 printk(BIOS_SPEW, "Non-burst video mode with sync pulses\n");
251 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
252 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
253 printk(BIOS_SPEW, "Non-burst video mode with sync events\n");
254 pkt_seq = pkt_seq_video_non_burst_sync_events;
255 } else {
256 printk(BIOS_SPEW, "Command mode\n");
257 pkt_seq = pkt_seq_command_mode;
258 }
259
260 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
261 if (err < 0)
262 return err;
263
264 err = tegra_dsi_get_format(dsi->format, &format);
265 if (err < 0)
266 return err;
267
268 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
269 DSI_CONTROL_LANES(dsi->lanes - 1) |
270 DSI_CONTROL_SOURCE(pipe);
271 tegra_dsi_writel(dsi, value, DSI_CONTROL);
272
273 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
274
275 value = DSI_HOST_CONTROL_HS;
276 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
277
278 value = tegra_dsi_readl(dsi, DSI_CONTROL);
279
280 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
281 value |= DSI_CONTROL_HS_CLK_CTRL;
282
283 value &= ~DSI_CONTROL_TX_TRIG(3);
284
285 /* enable DCS commands for command mode */
286 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
287 value &= ~DSI_CONTROL_DCS_ENABLE;
288 else
289 value |= DSI_CONTROL_DCS_ENABLE;
290
291 value |= DSI_CONTROL_VIDEO_ENABLE;
292 value &= ~DSI_CONTROL_HOST_ENABLE;
293 tegra_dsi_writel(dsi, value, DSI_CONTROL);
294
295 for (i = 0; i < NUM_PKT_SEQ; i++)
296 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
297
298 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
299 /* horizontal active pixels */
300 hact = mode->xres * mul / div;
301
302 /* horizontal sync width */
303 hsw = (hsync_end(mode) - hsync_start(mode)) * mul / div;
304 hsw -= 10;
305
306 /* horizontal back porch */
307 hbp = (htotal(mode) - hsync_end(mode)) * mul / div;
308 hbp -= 14;
309
310 /* horizontal front porch */
311 hfp = (hsync_start(mode) - mode->xres) * mul / div;
312 hfp -= 8;
313
314 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
315 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
316 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
317 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
318
319 /* set SOL delay (for non-burst mode only) */
320 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
321
322 /* TODO: implement ganged mode */
323 } else {
324 u16 bytes;
325 if (dsi->ganged_mode) {
326 /*
327 * For ganged mode, assume symmetric left-right mode.
328 */
329 bytes = 1 + (mode->xres / 2) * mul / div;
330 } else {
331 /* 1 byte (DCS command) + pixel data */
332 bytes = 1 + mode->xres * mul / div;
333 }
334
335 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
336 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
337 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
338 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
339
340 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
341 MIPI_DCS_WRITE_MEMORY_CONTINUE;
342 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
343
344 /* set SOL delay */
345 if (dsi->ganged_mode) {
346 unsigned long delay, bclk, bclk_ganged;
347 unsigned int lanes = dsi->ganged_lanes;
348
349 /* SOL to valid, valid to FIFO and FIFO write delay */
350 delay = 4 + 4 + 2;
351 delay = DIV_ROUND_UP(delay * mul, div * lanes);
352 /* FIFO read delay */
353 delay = delay + 6;
354
355 bclk = DIV_ROUND_UP(htotal(mode) * mul, div * lanes);
356 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
357 value = bclk - bclk_ganged + delay + 20;
358 } else {
359 /* TODO: revisit for non-ganged mode */
360 value = 8 * mul / div;
361 }
362
363 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
364 }
365
366 if (dsi->slave) {
367 err = tegra_dsi_configure(dsi->slave, pipe, mode);
368 if (err < 0)
369 return err;
370
371 /*
372 * enable ganged mode
373 */
374 if (dsi->ganged_mode) {
375 tegra_dsi_ganged_enable(dsi, mode->xres / 2,
376 mode->xres / 2);
377 tegra_dsi_ganged_enable(dsi->slave, 0, mode->xres / 2);
378 }
379 }
380 return 0;
381 }
382
383 static int tegra_output_dsi_enable(struct tegra_dsi *dsi,
384 const struct soc_nvidia_tegra132_config *config)
385 {
386 int err;
387
388 if (dsi->enabled)
389 return 0;
390
391 err = tegra_dsi_configure(dsi, 0, config);
392 if (err < 0)
393 return err;
394
395 /* enable DSI controller */
396 tegra_dsi_enable(dsi);
397
398 dsi->enabled = true;
399 return 0;
400 }
401
402
403 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
404 unsigned int vrefresh)
405 {
406 unsigned int timeout;
407 u32 value;
408
409 /* one frame high-speed transmission timeout */
410 timeout = (bclk / vrefresh) / 512;
411 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
412 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
413
414 /* 2 ms peripheral timeout for panel */
415 timeout = 2 * bclk / 512 * 1000;
416 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
417 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
418
419 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
420 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
421
422 if (dsi->slave)
423 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
424 }
425
426 static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi,
427 const struct soc_nvidia_tegra132_config *config)
428 {
429 unsigned int mul, div, num_lanes;
430 unsigned long bclk;
431 unsigned long pclk = config->pixel_clock;
432 int plld;
433 int err;
434 struct display_controller *disp_ctrl =
435 (void *)config->display_controller;
436 unsigned int shift_clk_div;
437
438 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
439 if (err < 0)
440 return err;
441
442 /*
443 * In ganged mode, account for the total number of lanes across both
444 * DSI channels so that the bit clock is properly computed.
445 */
446 if (dsi->ganged_mode)
447 num_lanes = dsi->ganged_lanes;
448 else
449 num_lanes = dsi->lanes;
450
451 /* compute byte clock */
452 bclk = (pclk * mul) / (div * num_lanes);
453
454 /*
455 * Compute bit clock and round up to the next MHz.
456 */
457 plld = DIV_ROUND_UP(bclk * 8, USECS_PER_SEC) * USECS_PER_SEC;
458
459 /*
460 * the actual rate on PLLD_OUT0 is 1/2 plld
461 */
462 dsi->clk_rate = plld / 2;
463 if (dsi->slave)
464 dsi->slave->clk_rate = dsi->clk_rate;
465
466 /* set up plld */
467 plld = clock_configure_plld(plld);
468 if (plld == 0) {
469 printk(BIOS_ERR, "%s: clock init failed\n", __func__);
470 return -1;
471 }
472
473 /*
474 * Derive pixel clock from bit clock using the shift clock divider.
475 * Note that this is only half of what we would expect, but we need
476 * that to make up for the fact that we divided the bit clock by a
477 * factor of two above.
478 */
479 shift_clk_div = ((8 * mul) / (div * num_lanes)) - 2;
480 update_display_shift_clock_divider(disp_ctrl, shift_clk_div);
481
482 tegra_dsi_set_timeout(dsi, bclk, config->refresh);
483 return plld/1000000;
484 }
485
486
487
488 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
489 {
490 unsigned long value;
491
492 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
493 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
494 return 0;
495 }
496
497 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
498 {
499 u32 value;
500
501 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
502 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
503 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
504 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
505 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
506
507 /* start calibration */
508 tegra_dsi_pad_enable(dsi);
509
510 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
511 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
512 DSI_PAD_OUT_CLK(0x0);
513 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
514
515 return tegra_mipi_calibrate(dsi->mipi);
516 }
517
518 static const char * const error_report[16] = {
519 "SoT Error",
520 "SoT Sync Error",
521 "EoT Sync Error",
522 "Escape Mode Entry Command Error",
523 "Low-Power Transmit Sync Error",
524 "Peripheral Timeout Error",
525 "False Control Error",
526 "Contention Detected",
527 "ECC Error, single-bit",
528 "ECC Error, multi-bit",
529 "Checksum Error",
530 "DSI Data Type Not Recognized",
531 "DSI VC ID Invalid",
532 "Invalid Transmission Length",
533 "Reserved",
534 "DSI Protocol Violation",
535 };
536
537 static int tegra_dsi_read_response(struct tegra_dsi *dsi,
538 const struct mipi_dsi_msg *msg,
539 unsigned int count)
540 {
541 u8 *rx = msg->rx_buf;
542 unsigned int i, j, k;
543 size_t size = 0;
544 u16 errors;
545 u32 value;
546
547 /* read and parse packet header */
548 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
549
550 switch (value & 0x3f) {
551 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
552 errors = (value >> 8) & 0xffff;
553 printk(BIOS_ERR, "Acknowledge and error report: %04x\n",
554 errors);
555 for (i = 0; i < ARRAY_SIZE(error_report); i++)
556 if (errors & BIT(i))
557 printk(BIOS_INFO, " %2u: %s\n", i,
558 error_report[i]);
559 break;
560
561 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
562 rx[0] = (value >> 8) & 0xff;
563 break;
564
565 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
566 rx[0] = (value >> 8) & 0xff;
567 rx[1] = (value >> 16) & 0xff;
568 break;
569
570 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
571 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
572 break;
573
574 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
575 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
576 break;
577
578 default:
579 printk(BIOS_ERR, "unhandled response type: %02x\n",
580 value & 0x3f);
581 break;
582 }
583
584 size = MIN(size, msg->rx_len);
585
586 if (msg->rx_buf && size > 0) {
587 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
588 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
589
590 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
591 rx[j + k] = (value >> (k << 3)) & 0xff;
592 }
593 }
594 return 0;
595 }
596
597 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout_ms)
598 {
599 u32 poll_interval_us = 2000;
600 u32 timeout_us = timeout_ms * 1000;
601
602 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
603 udelay(poll_interval_us);
604
605 do {
606 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
607 if ((value & DSI_TRIGGER_HOST) == 0)
608 return 0;
609
610 //usleep_range(1000, 2000);
611 if (timeout_us > poll_interval_us)
612 timeout_us -= poll_interval_us;
613 else
614 break;
615
616 udelay(poll_interval_us);
617 } while (1);
618
619 printk(BIOS_ERR, "%s: ERROR: timeout waiting for transmission"
620 " to complete\n", __func__);
621 return -ETIMEDOUT;
622 }
623
624 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
625 unsigned long timeout_ms)
626 {
627 u32 poll_interval_us = 2000;
628 u32 timeout_us = timeout_ms * 1000;
629
630 do {
631 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
632 u8 count = value & 0x1f;
633
634 if (count > 0)
635 return count;
636
637 if (timeout_us > poll_interval_us)
638 timeout_us -= poll_interval_us;
639 else
640 break;
641
642 udelay(poll_interval_us);
643 } while (1);
644
645 printk(BIOS_ERR, "%s: ERROR: timeout\n", __func__);
646
647 return -ETIMEDOUT;
648 }
649
650 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
651 const struct mipi_dsi_msg *msg)
652 {
653 struct tegra_dsi *dsi = host_to_tegra(host);
654 const u8 *tx = msg->tx_buf;
655 unsigned int count, i, j;
656 u32 value;
657 int err;
658
659 if (msg->tx_len > dsi->video_fifo_depth * 4)
660 return -ENOSPC;
661
662 /* reset underflow/overflow flags */
663 value = tegra_dsi_readl(dsi, DSI_STATUS);
664 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
665 value = DSI_HOST_CONTROL_FIFO_RESET;
666 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
667 udelay(20); // usleep_range(10, 20);
668 }
669
670 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
671 value |= DSI_POWER_CONTROL_ENABLE;
672 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
673
674 udelay(7000); //usleep_range(5000, 10000);
675
676 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
677 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
678
679 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
680 value |= DSI_HOST_CONTROL_HS;
681
682 /*
683 * The host FIFO has a maximum of 64 words, so larger transmissions
684 * need to use the video FIFO.
685 */
686 if (msg->tx_len > dsi->host_fifo_depth * 4)
687 value |= DSI_HOST_CONTROL_FIFO_SEL;
688
689 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
690
691 /*
692 * For reads and messages with explicitly requested ACK, generate a
693 * BTA sequence after the transmission of the packet.
694 */
695 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
696 (msg->rx_buf && msg->rx_len > 0)) {
697 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
698 value |= DSI_HOST_CONTROL_PKT_BTA;
699 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
700 }
701
702 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
703 tegra_dsi_writel(dsi, value, DSI_CONTROL);
704
705 /* write packet header */
706 value = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f);
707
708 if (tx && msg->tx_len > 0)
709 value |= tx[0] << 8;
710
711 if (tx && msg->tx_len > 1)
712 value |= tx[1] << 16;
713
714 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
715
716 /* write payload (if any) */
717 if (msg->tx_len > 2) {
718 for (j = 2; j < msg->tx_len; j += 4) {
719 value = 0;
720
721 for (i = 0; i < 4 && j + i < msg->tx_len; i++)
722 value |= tx[j + i] << (i << 3);
723
724 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
725 }
726 }
727
728 err = tegra_dsi_transmit(dsi, 250);
729 if (err < 0)
730 return err;
731
732 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
733 (msg->rx_buf && msg->rx_len > 0)) {
734 err = tegra_dsi_wait_for_response(dsi, 250);
735 if (err < 0)
736 return err;
737
738 count = err;
739
740 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
741 switch (value) {
742 case 0x84:
743 /*
744 dev_dbg(dsi->dev, "ACK\n");
745 */
746 break;
747
748 case 0x87:
749 /*
750 dev_dbg(dsi->dev, "ESCAPE\n");
751 */
752 break;
753
754 default:
755 printk(BIOS_INFO, "unknown status: %08x\n", value);
756 break;
757 }
758
759 if (count > 1) {
760 err = tegra_dsi_read_response(dsi, msg, count);
761 if (err < 0)
762 printk(BIOS_INFO,
763 "failed to parse response: %d\n",
764 err);
765 }
766 }
767 return 0;
768 }
769
770 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi,
771 struct tegra_dsi *slave)
772 {
773 /*
774 * The number of ganged lanes is the sum of lanes of all peripherals
775 * in the gang.
776 */
777 dsi->slave->ganged_lanes = dsi->lanes + dsi->slave->lanes;
778 dsi->slave->ganged_mode = 1;
779
780 dsi->ganged_lanes = dsi->lanes + dsi->slave->lanes;
781 dsi->ganged_mode = 1;
782 return 0;
783 }
784
785 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
786 struct mipi_dsi_device *device)
787 {
788 struct tegra_dsi *dsi = host_to_tegra(host);
789 int err;
790
791 dsi->flags = device->mode_flags;
792 dsi->format = device->format;
793 dsi->lanes = device->lanes;
794
795 if (dsi->master) {
796 err = tegra_dsi_ganged_setup(dsi->master, dsi);
797 if (err < 0) {
798 printk(BIOS_ERR, "failed to set up ganged mode: %d\n",
799 err);
800 return err;
801 }
802 }
803 return 0;
804 }
805
806 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
807 .attach = tegra_dsi_host_attach,
808 .transfer = tegra_dsi_host_transfer,
809 };
810
811 static int dsi_probe_if(int dsi_index,
812 struct soc_nvidia_tegra132_config *config)
813 {
814 struct tegra_dsi *dsi = &dsi_data[dsi_index];
815 int err;
816
817 /*
818 * Set default value. Will be taken from attached device once detected
819 */
820 dsi->flags = 0;
821 dsi->format = MIPI_DSI_FMT_RGB888;
822 dsi->lanes = 4;
823
824 /* get tegra_mipi_device */
825 dsi->mipi = tegra_mipi_request(&mipi_device_data[dsi_index], dsi_index);
826
827 /* calibrate */
828 err = tegra_dsi_pad_calibrate(dsi);
829 if (err < 0) {
830 printk(BIOS_ERR, "MIPI calibration failed: %d\n", err);
831 return err;
832 }
833
834 dsi->host.ops = &tegra_dsi_host_ops;
835 err = mipi_dsi_host_register(&dsi->host);
836 if (err < 0) {
837 printk(BIOS_ERR, "failed to register DSI host: %d\n", err);
838 return err;
839 }
840
841 /* get panel */
842 dsi->panel = panel_jdi_dsi_probe((struct mipi_dsi_device *)dsi->host.dev);
843 if (IS_ERR_PTR(dsi->panel)) {
844 printk(BIOS_ERR, "failed to get dsi panel\n");
845 return -EPTR;
846 }
847 dsi->panel->mode = config;
848 return 0;
849 }
850
851 static int dsi_probe(struct soc_nvidia_tegra132_config *config)
852 {
853 dsi_probe_if(DSI_A, config);
854 dsi_probe_if(DSI_B, config);
855 return 0;
856 }
857
858 static int dsi_enable(struct soc_nvidia_tegra132_config *config)
859 {
860 struct tegra_dsi *dsi_a = &dsi_data[DSI_A];
861
862 dsi_probe(config);
863
864 /* set up clock and TimeOutRegisters */
865 tegra_output_dsi_setup_clock(dsi_a, config);
866
867 /* configure APB_MISC_GP_MIPI_PAD_CTRL_0 */
868 write32((unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0, DSIB_MODE_DSI);
869
870 /* configure phy interface timing registers */
871 tegra_dsi_set_phy_timing(dsi_a);
872
873 /* prepare panel */
874 panel_jdi_prepare(dsi_a->panel);
875
876 /* enable dsi */
877 if (tegra_output_dsi_enable(dsi_a, config)) {
878 printk(BIOS_ERR,"%s: Error: failed to enable dsi output.\n",
879 __func__);
880 return -1;
881 }
882
883 return 0;
884 }
885
886 void dsi_display_startup(device_t dev)
887 {
888 struct soc_nvidia_tegra132_config *config = dev->chip_info;
889 struct display_controller *disp_ctrl =
890 (void *)config->display_controller;
891 u32 plld_rate;
892
893 u32 framebuffer_size_mb = config->framebuffer_size / MiB;
894 u32 framebuffer_base_mb= config->framebuffer_base / MiB;
895
896 printk(BIOS_INFO, "%s: entry: disp_ctrl: %p.\n",
897 __func__, disp_ctrl);
898
899 if (disp_ctrl == NULL) {
900 printk(BIOS_ERR, "Error: No dc is assigned by dt.\n");
901 return;
902 }
903
904 if (framebuffer_size_mb == 0){
905 framebuffer_size_mb = ALIGN_UP(config->display_xres *
906 config->display_yres *
907 (config->framebuffer_bits_per_pixel / 8), MiB)/MiB;
908 }
909
910 config->framebuffer_size = framebuffer_size_mb * MiB;
911 config->framebuffer_base = framebuffer_base_mb * MiB;
912
913 /*
914 * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
915 * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
916 * update_display_mode() for detail.
917 */
918 /* set default plld */
919 plld_rate = clock_configure_plld(config->pixel_clock * 2);
920 if (plld_rate == 0) {
921 printk(BIOS_ERR, "dc: clock init failed\n");
922 return;
923 }
924
925 /* set disp1's clock source to PLLD_OUT0 */
926 clock_configure_source(disp1, PLLD, (plld_rate/KHz)/2);
927
928 /* Init dc */
929 if (tegra_dc_init(disp_ctrl)) {
930 printk(BIOS_ERR, "dc: init failed\n");
931 return;
932 }
933
934 /* Configure dc mode */
935 if (update_display_mode(disp_ctrl, config)) {
936 printk(BIOS_ERR, "dc: failed to configure display mode.\n");
937 return;
938 }
939
940 /* Configure and enable dsi controller and panel */
941 if (dsi_enable(config)) {
942 printk(BIOS_ERR, "%s: failed to enable dsi controllers.\n",
943 __func__);
944 return;
945 }
946
947 /* Set up window */
948 update_window(config);
949 printk(BIOS_INFO, "%s: display init done.\n", __func__);
950
951 /* Save panel information to cb tables */
952 pass_mode_info_to_payload(config);
953
954 /*
955 * After this point, it is payload's responsibility to allocate
956 * framebuffer and sets the base address to dc's
957 * WINBUF_START_ADDR register and enables window by setting dc's
958 * DISP_DISP_WIN_OPTIONS register.
959 */
960 }
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