src/soc/nvidia/tegra132/chip.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2015 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef __SOC_NVIDIA_TEGRA132_CHIP_H__
  17 #define __SOC_NVIDIA_TEGRA132_CHIP_H__
  18 #include <soc/addressmap.h>
  19 #include <stdint.h>
  20 #include <soc/nvidia/tegra/dc.h>
  21
  22 struct soc_nvidia_tegra132_config {
  23         /* Address to monitor if spintable employed. */
  24         uintptr_t spintable_addr;
  25
  26         /*
  27          * panel resolution
  28          *  The two parameters below provides dc about panel spec.
  29          */
  30         u32 xres;               /* the width of H display active area */
  31         u32 yres;               /* the height of V display active area */
  32         u32 framebuffer_bits_per_pixel;
  33         u32 color_depth;        /* color format */
  34
  35         u64 display_controller; /* dc block base address */
  36         u32 framebuffer_base;
  37
  38         /*
  39          * Technically, we can compute this. At the same time, some platforms
  40          * might want to specify a specific size for their own reasons. If it
  41          * is zero the soc code will compute it as
  42          * xres*yres*framebuffer_bits_per_pixel/8
  43          */
  44         u32 framebuffer_size;
  45
  46         /*
  47          * Framebuffer resolution
  48          *  The two parameters below provides dc about framebuffer's sdram size.
  49          *  When they are not the same as panel resolution, we need to program
  50          *  dc's DDA_INCREMENT and some other registers to resize dc output.
  51          */
  52         u32 display_xres;
  53         u32 display_yres;
  54
  55         int href_to_sync;       /* HSYNC position with respect to line start */
  56         int hsync_width;        /* the width of HSYNC pulses */
  57         int hback_porch;        /* the distance between HSYNC trailing edge to
  58                                    beginning of H display active area */
  59         int hfront_porch;       /* the distance between end of H display active
  60                                    area to the leading edge of HSYNC */
  61         int vref_to_sync;
  62         int vsync_width;
  63         int vback_porch;
  64         int vfront_porch;
  65         int refresh;            /* display refresh rate */
  66
  67         int pixel_clock;        /* dc pixel clock source rate */
  68
  69         u32 panel_bits_per_pixel;
  70
  71         /* dp specific fields */
  72         struct {
  73                 /* pwm to use to set display contrast */
  74                 int pwm;
  75
  76                 /* HPD related timing */
  77                 int vdd_to_hpd_delay_ms;
  78                 int hpd_unplug_min_us;
  79                 int hpd_plug_min_us;
  80                 int hpd_irq_min_us;
  81
  82                 /* The minimum link configuraton settings */
  83                 u32 lane_count;
  84                 u32 enhanced_framing;
  85                 u32 link_bw;
  86                 u32 drive_current;
  87                 u32 preemphasis;
  88                 u32 postcursor;
  89         } dp;
  90
  91         int win_opt;
  92         void *dc_data;
  93 };
  94
  95 #endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */