src/soc/nvidia/tegra/dc.h

   1 /*
   2  *  Copyright 2013 Google Inc.
   3  *  (C) Copyright 2010
   4  *  NVIDIA Corporation <www.nvidia.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef __SOC_NVIDIA_TEGRA_DC_H
  18 #define __SOC_NVIDIA_TEGRA_DC_H
  19 #include <device/device.h>
  20 #include <stddef.h>
  21 #include <types.h>
  22
  23 /* Register definitions for the Tegra display controller */
  24
  25 /* CMD register 0x000 ~ 0x43 */
  26 struct dc_cmd_reg {
  27         /* Address 0x000 ~ 0x002 */
  28         u32 gen_incr_syncpt;            /* _CMD_GENERAL_INCR_SYNCPT_0 */
  29         u32 gen_incr_syncpt_ctrl;       /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
  30         u32 gen_incr_syncpt_err;        /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
  31
  32         u32 reserved0[5];               /* reserved_0[5] */
  33
  34         /* Address 0x008 ~ 0x00a */
  35         u32 win_a_incr_syncpt;          /* _CMD_WIN_A_INCR_SYNCPT_0 */
  36         u32 win_a_incr_syncpt_ctrl;     /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
  37         u32 win_a_incr_syncpt_err;      /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
  38
  39         u32 reserved1[5];               /* reserved_1[5] */
  40
  41         /* Address 0x010 ~ 0x012 */
  42         u32 win_b_incr_syncpt;          /* _CMD_WIN_B_INCR_SYNCPT_0 */
  43         u32 win_b_incr_syncpt_ctrl;     /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
  44         u32 win_b_incr_syncpt_err;      /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */
  45
  46         u32 reserved2[5];               /* reserved_2[5] */
  47
  48         /* Address 0x018 ~ 0x01a */
  49         u32 win_c_incr_syncpt;          /* _CMD_WIN_C_INCR_SYNCPT_0 */
  50         u32 win_c_incr_syncpt_ctrl;     /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */
  51         u32 win_c_incr_syncpt_err;      /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */
  52
  53         u32 reserved3[13];              /* reserved_3[13] */
  54
  55         /* Address 0x028 */
  56         u32 cont_syncpt_vsync;          /* _CMD_CONT_SYNCPT_VSYNC_0 */
  57
  58         u32 reserved4[7];               /* reserved_4[7] */
  59
  60         /* Address 0x030 ~ 0x033 */
  61         u32 ctxsw;                      /* _CMD_CTXSW_0 */
  62         u32 disp_cmd_opt0;              /* _CMD_DISPLAY_COMMAND_OPTION0_0 */
  63         u32 disp_cmd;                   /* _CMD_DISPLAY_COMMAND_0 */
  64         u32 sig_raise;                  /* _CMD_SIGNAL_RAISE_0 */
  65
  66         u32 reserved5[2];               /* reserved_0[2] */
  67
  68         /* Address 0x036 ~ 0x03e */
  69         u32 disp_pow_ctrl;              /* _CMD_DISPLAY_POWER_CONTROL_0 */
  70         u32 int_stat;                   /* _CMD_INT_STATUS_0 */
  71         u32 int_mask;                   /* _CMD_INT_MASK_0 */
  72         u32 int_enb;                    /* _CMD_INT_ENABLE_0 */
  73         u32 int_type;                   /* _CMD_INT_TYPE_0 */
  74         u32 int_polarity;               /* _CMD_INT_POLARITY_0 */
  75         u32 sig_raise1;         /* _CMD_SIGNAL_RAISE1_0 */
  76         u32 sig_raise2;         /* _CMD_SIGNAL_RAISE2_0 */
  77         u32 sig_raise3;         /* _CMD_SIGNAL_RAISE3_0 */
  78
  79         u32 reserved6;                  /* reserved_6 */
  80
  81         /* Address 0x040 ~ 0x043 */
  82         u32 state_access;               /* _CMD_STATE_ACCESS_0 */
  83         u32 state_ctrl;                 /* _CMD_STATE_CONTROL_0 */
  84         u32 disp_win_header;            /* _CMD_DISPLAY_WINDOW_HEADER_0 */
  85         u32 reg_act_ctrl;               /* _CMD_REG_ACT_CONTROL_0 */
  86 };
  87 check_member(dc_cmd_reg, reg_act_ctrl, 0x43 * 4);
  88
  89 enum {
  90         PIN_REG_COUNT           = 4,
  91         PIN_OUTPUT_SEL_COUNT    = 7,
  92 };
  93
  94 /* COM register 0x300 ~ 0x329 */
  95 struct dc_com_reg {
  96         /* Address 0x300 ~ 0x301 */
  97         u32 crc_ctrl;                   /* _COM_CRC_CONTROL_0 */
  98         u32 crc_checksum;               /* _COM_CRC_CHECKSUM_0 */
  99
 100         /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */
 101         u32 pin_output_enb[PIN_REG_COUNT];
 102
 103         /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */
 104         u32 pin_output_polarity[PIN_REG_COUNT];
 105
 106         /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */
 107         u32 pin_output_data[PIN_REG_COUNT];
 108
 109         /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */
 110         u32 pin_input_enb[PIN_REG_COUNT];
 111
 112         /* Address 0x312 ~ 0x313 */
 113         u32 pin_input_data0;            /* _COM_PIN_INPUT_DATA0_0 */
 114         u32 pin_input_data1;            /* _COM_PIN_INPUT_DATA1_0 */
 115
 116         /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */
 117         u32 pin_output_sel[PIN_OUTPUT_SEL_COUNT];
 118
 119         /* Address 0x31b ~ 0x329 */
 120         u32 pin_misc_ctrl;              /* _COM_PIN_MISC_CONTROL_0 */
 121         u32 pm0_ctrl;                   /* _COM_PM0_CONTROL_0 */
 122         u32 pm0_duty_cycle;             /* _COM_PM0_DUTY_CYCLE_0 */
 123         u32 pm1_ctrl;                   /* _COM_PM1_CONTROL_0 */
 124         u32 pm1_duty_cycle;             /* _COM_PM1_DUTY_CYCLE_0 */
 125         u32 spi_ctrl;                   /* _COM_SPI_CONTROL_0 */
 126         u32 spi_start_byte;             /* _COM_SPI_START_BYTE_0 */
 127         u32 hspi_wr_data_ab;            /* _COM_HSPI_WRITE_DATA_AB_0 */
 128         u32 hspi_wr_data_cd;            /* _COM_HSPI_WRITE_DATA_CD */
 129         u32 hspi_cs_dc;         /* _COM_HSPI_CS_DC_0 */
 130         u32 scratch_reg_a;              /* _COM_SCRATCH_REGISTER_A_0 */
 131         u32 scratch_reg_b;              /* _COM_SCRATCH_REGISTER_B_0 */
 132         u32 gpio_ctrl;                  /* _COM_GPIO_CTRL_0 */
 133         u32 gpio_debounce_cnt;          /* _COM_GPIO_DEBOUNCE_COUNTER_0 */
 134         u32 crc_checksum_latched;       /* _COM_CRC_CHECKSUM_LATCHED_0 */
 135 };
 136 check_member(dc_com_reg, crc_checksum_latched, (0x329 - 0x300) * 4);
 137
 138 enum dc_disp_h_pulse_pos {
 139         H_PULSE0_POSITION_A,
 140         H_PULSE0_POSITION_B,
 141         H_PULSE0_POSITION_C,
 142         H_PULSE0_POSITION_D,
 143         H_PULSE0_POSITION_COUNT,
 144 };
 145
 146 struct _disp_h_pulse {
 147         /* _DISP_H_PULSE0/1/2_CONTROL_0 */
 148         u32 h_pulse_ctrl;
 149         /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */
 150         u32 h_pulse_pos[H_PULSE0_POSITION_COUNT];
 151 };
 152
 153 enum dc_disp_v_pulse_pos {
 154         V_PULSE0_POSITION_A,
 155         V_PULSE0_POSITION_B,
 156         V_PULSE0_POSITION_C,
 157         V_PULSE0_POSITION_COUNT,
 158 };
 159
 160 struct _disp_v_pulse0 {
 161         /* _DISP_H_PULSE0/1_CONTROL_0 */
 162         u32 v_pulse_ctrl;
 163         /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */
 164         u32 v_pulse_pos[V_PULSE0_POSITION_COUNT];
 165 };
 166
 167 struct _disp_v_pulse2 {
 168         /* _DISP_H_PULSE2/3_CONTROL_0 */
 169         u32 v_pulse_ctrl;
 170         /* _DISP_H_PULSE2/3_POSITION_A_0 */
 171         u32 v_pulse_pos_a;
 172 };
 173
 174 enum dc_disp_h_pulse_reg {
 175         H_PULSE0,
 176         H_PULSE1,
 177         H_PULSE2,
 178         H_PULSE_COUNT,
 179 };
 180
 181 enum dc_disp_pp_select {
 182         PP_SELECT_A,
 183         PP_SELECT_B,
 184         PP_SELECT_C,
 185         PP_SELECT_D,
 186         PP_SELECT_COUNT,
 187 };
 188
 189 /* DISP register 0x400 ~ 0x4c1 */
 190 struct dc_disp_reg {
 191         /* Address 0x400 ~ 0x40a */
 192         u32 disp_signal_opt0;           /* _DISP_DISP_SIGNAL_OPTIONS0_0 */
 193         u32 rsvd_401;
 194         u32 disp_win_opt;               /* _DISP_DISP_WIN_OPTIONS_0 */
 195         u32 rsvd_403[2];                /* 403 - 404 */
 196         u32 disp_timing_opt;            /* _DISP_DISP_TIMING_OPTIONS_0 */
 197         u32 ref_to_sync;                /* _DISP_REF_TO_SYNC_0 */
 198         u32 sync_width;                 /* _DISP_SYNC_WIDTH_0 */
 199         u32 back_porch;                 /* _DISP_BACK_PORCH_0 */
 200         u32 disp_active;                /* _DISP_DISP_ACTIVE_0 */
 201         u32 front_porch;                /* _DISP_FRONT_PORCH_0 */
 202
 203         /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_  */
 204         struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
 205
 206         /* Address 0x41a ~ 0x421 */
 207         struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */
 208         struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */
 209
 210         /* Address 0x422 ~ 0x425 */
 211         struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */
 212         struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */
 213
 214         u32 rsvd_426[8];                /* 426 - 42d */
 215
 216         /* Address 0x42e ~ 0x430 */
 217         u32 disp_clk_ctrl;              /* _DISP_DISP_CLOCK_CONTROL_0 */
 218         u32 disp_interface_ctrl;        /* _DISP_DISP_INTERFACE_CONTROL_0 */
 219         u32 disp_color_ctrl;            /* _DISP_DISP_COLOR_CONTROL_0 */
 220
 221         u32 rsvd_431[6];                /* 431 - 436 */
 222
 223         /* Address 0x437 ~ 0x439 */
 224         u32 color_key0_upper;           /* _DISP_COLOR_KEY0_UPPER_0 */
 225         u32 color_key1_lower;           /* _DISP_COLOR_KEY1_LOWER_0 */
 226         u32 color_key1_upper;           /* _DISP_COLOR_KEY1_UPPER_0 */
 227
 228         u32 reserved0[2];               /* 43a - 43b */
 229
 230         /* Address 0x43c ~ 0x441 */
 231         u32 cursor_foreground;          /* _DISP_CURSOR_FOREGROUND_0 */
 232         u32 cursor_background;          /* _DISP_CURSOR_BACKGROUND_0 */
 233         u32 cursor_start_addr;          /* _DISP_CURSOR_START_ADDR_0 */
 234         u32 cursor_start_addr_ns;       /* _DISP_CURSOR_START_ADDR_NS_0 */
 235         u32 cursor_pos;         /* _DISP_CURSOR_POSITION_0 */
 236         u32 cursor_pos_ns;              /* _DISP_CURSOR_POSITION_NS_0 */
 237
 238         u32 rsvd_442[62];               /* 442 - 47f */
 239
 240         /* Address 0x480 ~ 0x483 */
 241         u32 dc_mccif_fifoctrl;          /* _DISP_DC_MCCIF_FIFOCTRL_0 */
 242         u32 mccif_disp0a_hyst;          /* _DISP_MCCIF_DISPLAY0A_HYST_0 */
 243         u32 mccif_disp0b_hyst;          /* _DISP_MCCIF_DISPLAY0B_HYST_0 */
 244         u32 mccif_disp0c_hyst;          /* _DISP_MCCIF_DISPLAY0C_HYST_0 */
 245
 246         u32 rsvd_484[61];               /* 484 - 4c0 */
 247
 248         /* Address 0x4c1 */
 249         u32 disp_misc_ctrl;             /* _DISP_DISP_MISC_CONTROL_0 */
 250
 251         u32 rsvd_4c2[34];               /* 4c2 - 4e3 */
 252
 253         /* Address 0x4e4 */
 254         u32 blend_background_color;     /* _DISP_BLEND_BACKGROUND_COLOR_0 */
 255 };
 256 check_member(dc_disp_reg, blend_background_color, (0x4e4 - 0x400) * 4);
 257
 258 enum dc_winc_filter_p {
 259         WINC_FILTER_COUNT       = 0x10,
 260 };
 261
 262 /* Window A/B/C register 0x500 ~ 0x628 */
 263 struct dc_winc_reg {
 264
 265         /* Address 0x500 */
 266         u32 color_palette;              /* _WINC_COLOR_PALETTE_0 */
 267
 268         u32 reserved0[0xff];            /* reserved_0[0xff] */
 269
 270         /* Address 0x600 */
 271         u32 palette_color_ext;          /* _WINC_PALETTE_COLOR_EXT_0 */
 272
 273         /* _WINC_H_FILTER_P00~0F_0 */
 274         /* Address 0x601 ~ 0x610 */
 275         u32 h_filter_p[WINC_FILTER_COUNT];
 276
 277         /* Address 0x611 ~ 0x618 */
 278         u32 csc_yof;                    /* _WINC_CSC_YOF_0 */
 279         u32 csc_kyrgb;                  /* _WINC_CSC_KYRGB_0 */
 280         u32 csc_kur;                    /* _WINC_CSC_KUR_0 */
 281         u32 csc_kvr;                    /* _WINC_CSC_KVR_0 */
 282         u32 csc_kug;                    /* _WINC_CSC_KUG_0 */
 283         u32 csc_kvg;                    /* _WINC_CSC_KVG_0 */
 284         u32 csc_kub;                    /* _WINC_CSC_KUB_0 */
 285         u32 csc_kvb;                    /* _WINC_CSC_KVB_0 */
 286
 287         /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
 288         u32 v_filter_p[WINC_FILTER_COUNT];
 289 };
 290 check_member(dc_winc_reg, v_filter_p, (0x619 - 0x500) * 4);
 291
 292 /* WIN A/B/C Register 0x700 ~ 0x719*/
 293 struct dc_win_reg {
 294         /* Address 0x700 ~ 0x719 */
 295         u32 win_opt;                    /* _WIN_WIN_OPTIONS_0 */
 296         u32 byte_swap;                  /* _WIN_BYTE_SWAP_0 */
 297         u32 buffer_ctrl;                /* _WIN_BUFFER_CONTROL_0 */
 298         u32 color_depth;                /* _WIN_COLOR_DEPTH_0 */
 299         u32 pos;                        /* _WIN_POSITION_0 */
 300         u32 size;                       /* _WIN_SIZE_0 */
 301         u32 prescaled_size;             /* _WIN_PRESCALED_SIZE_0 */
 302         u32 h_initial_dda;              /* _WIN_H_INITIAL_DDA_0 */
 303         u32 v_initial_dda;              /* _WIN_V_INITIAL_DDA_0 */
 304         u32 dda_increment;              /* _WIN_DDA_INCREMENT_0 */
 305         u32 line_stride;                /* _WIN_LINE_STRIDE_0 */
 306         u32 buf_stride;                 /* _WIN_BUF_STRIDE_0 */
 307         u32 uv_buf_stride;              /* _WIN_UV_BUF_STRIDE_0 */
 308         u32 buffer_addr_mode;           /* _WIN_BUFFER_ADDR_MODE_0 */
 309         u32 dv_ctrl;                    /* _WIN_DV_CONTROL_0 */
 310         u32 blend_nokey;                /* _WIN_BLEND_NOKEY_0 */
 311         u32 blend_1win;                 /* _WIN_BLEND_1WIN_0 */
 312         u32 blend_2win_x;               /* _WIN_BLEND_2WIN_X_0 */
 313         u32 blend_2win_y;               /* _WIN_BLEND_2WIN_Y_0 */
 314         u32 blend_3win_xy;              /* _WIN_BLEND_3WIN_XY_0 */
 315         u32 hp_fetch_ctrl;              /* _WIN_HP_FETCH_CONTROL_0 */
 316         u32 global_alpha;               /* _WIN_GLOBAL_ALPHA */
 317         u32 blend_layer_ctrl;           /* _WINBUF_BLEND_LAYER_CONTROL_0 */
 318         u32 blend_match_select;         /* _WINBUF_BLEND_MATCH_SELECT_0 */
 319         u32 blend_nomatch_select;       /* _WINBUF_BLEND_NOMATCH_SELECT_0 */
 320         u32 blend_alpha_1bit;           /* _WINBUF_BLEND_ALPHA_1BIT_0 */
 321 };
 322 check_member(dc_win_reg, blend_alpha_1bit, (0x719 - 0x700) * 4);
 323
 324 /* WINBUF A/B/C Register 0x800 ~ 0x80d */
 325 struct dc_winbuf_reg {
 326         /* Address 0x800 ~ 0x80d */
 327         u32 start_addr;         /* _WINBUF_START_ADDR_0 */
 328         u32 start_addr_ns;              /* _WINBUF_START_ADDR_NS_0 */
 329         u32 start_addr_u;               /* _WINBUF_START_ADDR_U_0 */
 330         u32 start_addr_u_ns;            /* _WINBUF_START_ADDR_U_NS_0 */
 331         u32 start_addr_v;               /* _WINBUF_START_ADDR_V_0 */
 332         u32 start_addr_v_ns;            /* _WINBUF_START_ADDR_V_NS_0 */
 333         u32 addr_h_offset;              /* _WINBUF_ADDR_H_OFFSET_0 */
 334         u32 addr_h_offset_ns;           /* _WINBUF_ADDR_H_OFFSET_NS_0 */
 335         u32 addr_v_offset;              /* _WINBUF_ADDR_V_OFFSET_0 */
 336         u32 addr_v_offset_ns;           /* _WINBUF_ADDR_V_OFFSET_NS_0 */
 337         u32 uflow_status;               /* _WINBUF_UFLOW_STATUS_0 */
 338         u32 buffer_surface_kind;        /* DC_WIN_BUFFER_SURFACE_KIND */
 339         u32 rsvd_80c;
 340         u32 start_addr_hi;              /* DC_WINBUF_START_ADDR_HI_0 */
 341 };
 342 check_member(dc_winbuf_reg, start_addr_hi, (0x80d - 0x800) * 4);
 343
 344 /* Display Controller (DC_) regs */
 345 struct display_controller {
 346         struct dc_cmd_reg cmd;          /* CMD register 0x000 ~ 0x43 */
 347         u32 reserved0[0x2bc];
 348
 349         struct dc_com_reg com;          /* COM register 0x300 ~ 0x329 */
 350         u32 reserved1[0xd6];
 351
 352         struct dc_disp_reg disp;        /* DISP register 0x400 ~ 0x4e4 */
 353         u32 reserved2[0x1b];
 354
 355         struct dc_winc_reg winc;        /* Window A/B/C 0x500 ~ 0x628 */
 356         u32 reserved3[0xd7];
 357
 358         struct dc_win_reg win;          /* WIN A/B/C 0x700 ~ 0x719*/
 359         u32 reserved4[0xe6];
 360
 361         struct dc_winbuf_reg winbuf;    /* WINBUF A/B/C 0x800 ~ 0x80d */
 362 };
 363 check_member(display_controller, winbuf, 0x800 * 4);
 364
 365
 366 /* DC_CMD_DISPLAY_COMMAND 0x032 */
 367 #define  DISP_COMMAND_RAISE                     (1 << 0)
 368 #define  DISP_CTRL_MODE_STOP                    (0 << 5)
 369 #define  DISP_CTRL_MODE_C_DISPLAY               (1 << 5)
 370 #define  DISP_CTRL_MODE_NC_DISPLAY              (2 << 5)
 371 #define  DISP_COMMAND_RAISE_VECTOR(x)           (((x) & 0x1f) << 22)
 372 #define  DISP_COMMAND_RAISE_CHANNEL_ID(x)       (((x) & 0xf) << 27)
 373
 374 /* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */
 375 #define PW0_ENABLE              BIT(0)
 376 #define PW1_ENABLE              BIT(2)
 377 #define PW2_ENABLE              BIT(4)
 378 #define PW3_ENABLE              BIT(6)
 379 #define PW4_ENABLE              BIT(8)
 380 #define PM0_ENABLE              BIT(16)
 381 #define PM1_ENABLE              BIT(18)
 382 #define SPI_ENABLE              BIT(24)
 383 #define HSPI_ENABLE             BIT(25)
 384
 385 /* DC_CMD_STATE_ACCESS 0x040 */
 386 #define  READ_MUX_ASSEMBLY      (0 << 0)
 387 #define  READ_MUX_ACTIVE        (1 << 0)
 388 #define  WRITE_MUX_ASSEMBLY     (0 << 2)
 389 #define  WRITE_MUX_ACTIVE       (1 << 2)
 390
 391 /* DC_CMD_STATE_CONTROL 0x041 */
 392 #define GENERAL_ACT_REQ         BIT(0)
 393 #define WIN_A_ACT_REQ           BIT(1)
 394 #define WIN_B_ACT_REQ           BIT(2)
 395 #define WIN_C_ACT_REQ           BIT(3)
 396 #define WIN_D_ACT_REQ           BIT(4)
 397 #define WIN_H_ACT_REQ           BIT(5)
 398 #define CURSOR_ACT_REQ          BIT(7)
 399 #define GENERAL_UPDATE          BIT(8)
 400 #define WIN_A_UPDATE            BIT(9)
 401 #define WIN_B_UPDATE            BIT(10)
 402 #define WIN_C_UPDATE            BIT(11)
 403 #define WIN_D_UPDATE            BIT(12)
 404 #define WIN_H_UPDATE            BIT(13)
 405 #define CURSOR_UPDATE           BIT(15)
 406 #define NC_HOST_TRIG            BIT(24)
 407
 408 /* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
 409 #define WINDOW_A_SELECT         BIT(4)
 410 #define WINDOW_B_SELECT         BIT(5)
 411 #define WINDOW_C_SELECT         BIT(6)
 412 #define WINDOW_D_SELECT         BIT(7)
 413 #define WINDOW_H_SELECT         BIT(8)
 414
 415 /* DC_DISP_DISP_WIN_OPTIONS 0x402 */
 416 #define CURSOR_ENABLE           BIT(16)
 417 #define SOR_ENABLE              BIT(25)
 418 #define TVO_ENABLE              BIT(28)
 419 #define DSI_ENABLE              BIT(29)
 420 #define HDMI_ENABLE             BIT(30)
 421
 422 /* DC_DISP_DISP_TIMING_OPTIONS 0x405 */
 423 #define VSYNC_H_POSITION(x)     ((x) & 0xfff)
 424
 425 /* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
 426 #define SHIFT_CLK_DIVIDER_SHIFT 0
 427 #define SHIFT_CLK_DIVIDER_MASK  (0xff << SHIFT_CLK_DIVIDER_SHIFT)
 428 #define PIXEL_CLK_DIVIDER_SHIFT 8
 429 #define PIXEL_CLK_DIVIDER_MSK   (0xf << PIXEL_CLK_DIVIDER_SHIFT)
 430 enum {
 431         PIXEL_CLK_DIVIDER_PCD1,
 432         PIXEL_CLK_DIVIDER_PCD1H,
 433         PIXEL_CLK_DIVIDER_PCD2,
 434         PIXEL_CLK_DIVIDER_PCD3,
 435         PIXEL_CLK_DIVIDER_PCD4,
 436         PIXEL_CLK_DIVIDER_PCD6,
 437         PIXEL_CLK_DIVIDER_PCD8,
 438         PIXEL_CLK_DIVIDER_PCD9,
 439         PIXEL_CLK_DIVIDER_PCD12,
 440         PIXEL_CLK_DIVIDER_PCD16,
 441         PIXEL_CLK_DIVIDER_PCD18,
 442         PIXEL_CLK_DIVIDER_PCD24,
 443         PIXEL_CLK_DIVIDER_PCD13,
 444 };
 445 #define  SHIFT_CLK_DIVIDER(x)           (((x) - 1) * 2)
 446
 447 /* DC_WIN_WIN_OPTIONS 0x700 */
 448 #define  H_DIRECTION_DECREMENT(x)       ((x) << 0)
 449 #define  V_DIRECTION_DECREMENT(x)       ((x) << 2)
 450 #define  WIN_SCAN_COLUMN                BIT(4)
 451 #define  COLOR_EXPAND                   BIT(6)
 452 #define  H_FILTER_ENABLE(x)             ((x) << 8)
 453 #define  V_FILTER_ENABLE(x)             ((x) << 10)
 454 #define  CP_ENABLE                      BIT(16)
 455 #define  CSC_ENABLE                     BIT(18)
 456 #define  DV_ENABLE                      BIT(20)
 457 #define  INTERLACE_ENABLE               BIT(23)
 458 #define  INTERLACE_DISABLE              (0 << 23)
 459 #define  WIN_ENABLE                     BIT(30)
 460
 461 /* _WIN_COLOR_DEPTH_0 0x703 */
 462 enum {
 463         COLOR_DEPTH_P8 = 3,
 464         COLOR_DEPTH_B4G4R4A4,
 465         COLOR_DEPTH_B5G5R5A,
 466         COLOR_DEPTH_B5G6R5,
 467         COLOR_DEPTH_AB5G5R5,
 468         COLOR_DEPTH_B8G8R8A8 = 12,
 469         COLOR_DEPTH_R8G8B8A8,
 470         COLOR_DEPTH_YCbCr422 = 16,
 471         COLOR_DEPTH_YUV422,
 472         COLOR_DEPTH_YCbCr420P,
 473         COLOR_DEPTH_YUV420P,
 474         COLOR_DEPTH_YCbCr422P,
 475         COLOR_DEPTH_YUV422P,
 476         COLOR_DEPTH_N422R,
 477         COLOR_DEPTH_YCbCr422R = COLOR_DEPTH_N422R,
 478         COLOR_DEPTH_N422R_TRUE,
 479         COLOR_DEPTH_YUV422R = COLOR_DEPTH_N422R_TRUE,
 480         COLOR_DEPTH_CrYCbY422,
 481         COLOR_DEPTH_VYUY422,
 482 };
 483
 484 /* DC_WIN_DDA_INCREMENT 0x709 */
 485 #define DDA_INC(prescaled_size, post_scaled_size)       \
 486                 (((prescaled_size) - 1) * 0x1000 / ((post_scaled_size) - 1))
 487 #define H_DDA_INC(x)            (((x) & 0xffff) << 0)
 488 #define V_DDA_INC(x)            (((x) & 0xffff) << 16)
 489
 490 struct tegra_dc {
 491         void                            *config;
 492         void                            *out;
 493         void                            *base;
 494 };
 495
 496 struct tegra_dc_mode {
 497         int     pclk;
 498         int     rated_pclk;
 499         int     h_ref_to_sync;
 500         int     v_ref_to_sync;
 501         int     h_sync_width;
 502         int     v_sync_width;
 503         int     h_back_porch;
 504         int     v_back_porch;
 505         int     h_active;
 506         int     v_active;
 507         int     h_front_porch;
 508         int     v_front_porch;
 509         int     stereo_mode;
 510         u32     flags;
 511         u8      avi_m;
 512         u32     vmode;
 513 };
 514
 515 unsigned long READL(void * p);
 516 void WRITEL(unsigned long value, void * p);
 517
 518 #ifndef __PRE_RAM__
 519 void display_startup(device_t dev);
 520 #endif
 521 void dp_init(void * _config);
 522 void dp_enable(void * _dp);
 523 unsigned int fb_base_mb(void);
 524
 525 #endif /* __SOC_NVIDIA_TEGRA_DC_H */