src/soc/intel/skylake/smbus.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2014 Google Inc.
   6  * Copyright (C) 2015 Intel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <arch/io.h>
  19 #include <console/console.h>
  20 #include <device/device.h>
  21 #include <device/path.h>
  22 #include <device/smbus.h>
  23 #include <device/smbus_def.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include <device/pci_ops.h>
  27 #include <soc/iomap.h>
  28 #include <soc/ramstage.h>
  29 #include <soc/smbus.h>
  30
  31 static void pch_smbus_init(device_t dev)
  32 {
  33         struct resource *res;
  34         u16 reg16;
  35
  36         /* Enable clock gating */
  37         reg16 = pci_read_config32(dev, 0x80);
  38         reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
  39         pci_write_config32(dev, 0x80, reg16);
  40
  41         /* Set Receive Slave Address */
  42         res = find_resource(dev, PCI_BASE_ADDRESS_4);
  43         if (res)
  44                 outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
  45 }
  46
  47 static int lsmbus_read_byte(device_t dev, u8 address)
  48 {
  49         u16 device;
  50         struct resource *res;
  51         struct bus *pbus;
  52
  53         device = dev->path.i2c.device;
  54         pbus = get_pbus_smbus(dev);
  55         res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
  56
  57         return do_smbus_read_byte(res->base, device, address);
  58 }
  59
  60 static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
  61 {
  62         u16 device;
  63         struct resource *res;
  64         struct bus *pbus;
  65
  66         device = dev->path.i2c.device;
  67         pbus = get_pbus_smbus(dev);
  68         res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
  69         return do_smbus_write_byte(res->base, device, address, data);
  70 }
  71
  72 static struct smbus_bus_operations lops_smbus_bus = {
  73         .read_byte      = lsmbus_read_byte,
  74         .write_byte     = lsmbus_write_byte,
  75 };
  76
  77 static void smbus_read_resources(device_t dev)
  78 {
  79         struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
  80         res->base = SMBUS_BASE_ADDRESS;
  81         res->size = 32;
  82         res->limit = res->base + res->size - 1;
  83         res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
  84                      IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  85
  86         /* Also add MMIO resource */
  87         res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
  88 }
  89
  90 static struct device_operations smbus_ops = {
  91         .read_resources         = &smbus_read_resources,
  92         .set_resources          = &pci_dev_set_resources,
  93         .enable_resources       = &pci_dev_enable_resources,
  94         .scan_bus               = &scan_smbus,
  95         .init                   = &pch_smbus_init,
  96         .ops_smbus_bus          = &lops_smbus_bus,
  97         .ops_pci                = &soc_pci_ops,
  98 };
  99
 100 static const unsigned short pci_device_ids[] = {
 101         0x9d23, /* SunRisePoint LP */
 102         0
 103 };
 104
 105 static const struct pci_driver pch_smbus __pci_driver = {
 106         .ops     = &smbus_ops,
 107         .vendor  = PCI_VENDOR_ID_INTEL,
 108         .devices = pci_device_ids,
 109 };