src/soc/intel/skylake/romstage/smbus.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2014 Google Inc.
   6  * Copyright (C) 2015 Intel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <arch/io.h>
  19 #include <console/console.h>
  20 #include <device/pci_ids.h>
  21 #include <device/pci_def.h>
  22 #include <reg_script.h>
  23 #include <soc/iomap.h>
  24 #include <soc/pci_devs.h>
  25 #include <soc/smbus.h>
  26 #include <soc/romstage.h>
  27
  28 static const struct reg_script smbus_init_script[] = {
  29         /* Set SMBUS I/O base address */
  30         REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1),
  31         /* Set SMBUS enable */
  32         REG_PCI_WRITE8(HOSTC, HST_EN),
  33         /* Enable I/O access */
  34         REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO),
  35         /* Disable interrupts */
  36         REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
  37         /* Clear errors */
  38         REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
  39         /* Indicate the end of this array by REG_SCRIPT_END */
  40         REG_SCRIPT_END,
  41 };
  42
  43 void enable_smbus(void)
  44 {
  45         reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
  46 }
  47
  48 int smbus_read_byte(unsigned device, unsigned address)
  49 {
  50         return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address);
  51 }