src/soc/intel/skylake/romstage/power_state.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2014 Google Inc.
   5  * Copyright (C) 2015 Intel Corporation.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/early_variables.h>
  18 #include <arch/io.h>
  19 #include <cbmem.h>
  20 #include <console/console.h>
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <device/pci_def.h>
  24 #include <reg_script.h>
  25 #include <stdint.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <soc/iomap.h>
  29 #include <soc/pmc.h>
  30 #include <soc/pci_devs.h>
  31 #include <soc/pm.h>
  32 #include <soc/romstage.h>
  33
  34 static struct chipset_power_state power_state CAR_GLOBAL;
  35
  36 static void migrate_power_state(int is_recovery)
  37 {
  38         struct chipset_power_state *ps_cbmem;
  39         struct chipset_power_state *ps_car;
  40
  41         ps_car = car_get_var_ptr(&power_state);
  42         ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem));
  43
  44         if (ps_cbmem == NULL) {
  45                 printk(BIOS_DEBUG, "Not adding power state to cbmem!\n");
  46                 return;
  47         }
  48         memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
  49 }
  50 ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
  51
  52 /* Return 0, 3, or 5 to indicate the previous sleep state. */
  53 static uint32_t prev_sleep_state(struct chipset_power_state *ps)
  54 {
  55         /* Default to S0. */
  56         uint32_t prev_sleep_state = SLEEP_STATE_S0;
  57
  58         if (ps->pm1_sts & WAK_STS) {
  59                 switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
  60 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
  61                 case SLP_TYP_S3:
  62                         prev_sleep_state = SLEEP_STATE_S3;
  63                         break;
  64 #endif
  65                 case SLP_TYP_S5:
  66                         prev_sleep_state = SLEEP_STATE_S5;
  67                         break;
  68                 }
  69                 /* Clear SLP_TYP. */
  70                 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
  71         }
  72
  73         /*
  74          * If waking from S3 determine if deep S3 is enabled. If not,
  75          * need to check both deep sleep well and normal suspend well.
  76          * Otherwise just check deep sleep well.
  77          */
  78         if (prev_sleep_state == SLEEP_STATE_S3) {
  79                 /* PWR_FLR represents deep sleep power well loss. */
  80                 uint32_t mask = PWR_FLR;
  81
  82                 /* If deep s3 isn't enabled check the suspend well too. */
  83                 if (!deep_s3_enabled())
  84                         mask |= SUS_PWR_FLR;
  85
  86                 if (ps->gen_pmcon_b & mask)
  87                         prev_sleep_state = SLEEP_STATE_S5;
  88         }
  89
  90         return prev_sleep_state;
  91 }
  92
  93 static void dump_power_state(struct chipset_power_state *ps)
  94 {
  95         printk(BIOS_DEBUG, "PM1_STS:   %04x\n", ps->pm1_sts);
  96         printk(BIOS_DEBUG, "PM1_EN:    %04x\n", ps->pm1_en);
  97         printk(BIOS_DEBUG, "PM1_CNT:   %08x\n", ps->pm1_cnt);
  98         printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
  99                ps->tco1_sts, ps->tco2_sts);
 100
 101         printk(BIOS_DEBUG, "GPE0_STS:  %08x %08x %08x %08x\n",
 102                ps->gpe0_sts[0], ps->gpe0_sts[1],
 103                ps->gpe0_sts[2], ps->gpe0_sts[3]);
 104         printk(BIOS_DEBUG, "GPE0_EN:   %08x %08x %08x %08x\n",
 105                ps->gpe0_en[0], ps->gpe0_en[1],
 106                ps->gpe0_en[2], ps->gpe0_en[3]);
 107
 108         printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
 109                ps->gen_pmcon_a, ps->gen_pmcon_b);
 110
 111         printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 112                ps->gblrst_cause[0], ps->gblrst_cause[1]);
 113
 114         printk(BIOS_DEBUG, "Previous Sleep State: S%d\n",
 115                ps->prev_sleep_state);
 116 }
 117
 118 /* Fill power state structure from ACPI PM registers */
 119 struct chipset_power_state *fill_power_state(void)
 120 {
 121         uint16_t tcobase;
 122         uint8_t *pmc;
 123         struct chipset_power_state *ps = car_get_var_ptr(&power_state);
 124
 125         tcobase = pmc_tco_regs();
 126
 127         ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
 128         ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
 129         ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
 130         ps->tco1_sts = inw(tcobase + TCO1_STS);
 131         ps->tco2_sts = inw(tcobase + TCO2_STS);
 132         ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
 133         ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
 134         ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
 135         ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
 136         ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
 137         ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
 138         ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
 139         ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
 140
 141         ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
 142         ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
 143
 144         pmc = pmc_mmio_regs();
 145         ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
 146         ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
 147
 148         ps->prev_sleep_state = prev_sleep_state(ps);
 149
 150         dump_power_state(ps);
 151
 152         return ps;
 153 }