src/soc/intel/skylake/pcie.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2014 Google Inc.
   6  * Copyright (C) 2015 Intel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <chip.h>
  19 #include <console/console.h>
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pciexp.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <soc/gpio.h>
  26 #include <soc/lpc.h>
  27 #include <soc/pch.h>
  28 #include <soc/pci_devs.h>
  29 #include <soc/cpu.h>
  30 #include <delay.h>
  31
  32 static void pch_pcie_init(struct device *dev)
  33 {
  34         u16 reg16;
  35         u32 reg32;
  36
  37         printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
  38
  39         /* Enable SERR */
  40         reg32 = pci_read_config32(dev, PCI_COMMAND);
  41         reg32 |= PCI_COMMAND_SERR;
  42         pci_write_config32(dev, PCI_COMMAND, reg32);
  43
  44         /* Enable Bus Master */
  45         reg32 = pci_read_config32(dev, PCI_COMMAND);
  46         reg32 |= PCI_COMMAND_MASTER;
  47         pci_write_config32(dev, PCI_COMMAND, reg32);
  48
  49         /* Set Cache Line Size to 0x10 */
  50         pci_write_config8(dev, 0x0c, 0x10);
  51
  52         reg16 = pci_read_config16(dev, 0x3e);
  53         reg16 &= ~(1 << 0); /* disable parity error response */
  54         reg16 |= (1 << 2); /* ISA enable */
  55         pci_write_config16(dev, 0x3e, reg16);
  56
  57 #ifdef EVEN_MORE_DEBUG
  58         reg32 = pci_read_config32(dev, 0x20);
  59         printk(BIOS_SPEW, "    MBL    = 0x%08x\n", reg32);
  60         reg32 = pci_read_config32(dev, 0x24);
  61         printk(BIOS_SPEW, "    PMBL   = 0x%08x\n", reg32);
  62         reg32 = pci_read_config32(dev, 0x28);
  63         printk(BIOS_SPEW, "    PMBU32 = 0x%08x\n", reg32);
  64         reg32 = pci_read_config32(dev, 0x2c);
  65         printk(BIOS_SPEW, "    PMLU32 = 0x%08x\n", reg32);
  66 #endif
  67
  68         /* Clear errors in status registers */
  69         reg16 = pci_read_config16(dev, 0x06);
  70         pci_write_config16(dev, 0x06, reg16);
  71         reg16 = pci_read_config16(dev, 0x1e);
  72         pci_write_config16(dev, 0x1e, reg16);
  73 }
  74
  75 static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off)
  76 {
  77         /* Set max snoop and non-snoop latency for the SOC */
  78         pci_mmio_write_config32(dev, off, 0x10031003);
  79 }
  80
  81 static struct pci_operations pcie_ops = {
  82         .set_L1_ss_latency = pcie_set_L1_ss_max_latency,
  83 };
  84
  85 static struct device_operations device_ops = {
  86         .read_resources         = pci_bus_read_resources,
  87         .set_resources          = pci_dev_set_resources,
  88         .enable_resources       = pci_bus_enable_resources,
  89         .init                   = pch_pcie_init,
  90         .enable                 = NULL,
  91         .scan_bus               = pciexp_scan_bridge,
  92         .ops_pci                = &pcie_ops,
  93 };
  94
  95 static const unsigned short pcie_device_ids[] = {
  96         /* Sunrisepoint-LP */
  97         0x9d10, 0x9d11, 0x9d12, 0x9d13, 0x9d14, 0x9d15, 0x9d16, 0x9d17,
  98         0x9d18, 0x9d19, 0x9d1a, 0x9d1b,
  99         0
 100 };
 101
 102 static const struct pci_driver pch_pcie __pci_driver = {
 103         .ops     = &device_ops,
 104         .vendor  = PCI_VENDOR_ID_INTEL,
 105         .devices = pcie_device_ids,
 106 };