| blob | 41e1a9d75e3e8ec89e3f94f2b1358ffb8f7b629f |
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2014 Google Inc.
6 * Copyright (C) 2015 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
18 #include <soc/interrupt.h>
19 #include <soc/irq.h>
21 Name (PICP, Package () {
22 /* D31: cAVS, SMBus, GbE, Nothpeak */
23 Package () { 0x001FFFFF, 0, 0, cAVS_INTA_IRQ },
24 Package () { 0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },
25 Package () { 0x001FFFFF, 2, 0, GbE_INTC_IRQ },
26 Package () { 0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },
27 /* D30: SerialIo and SCS */
28 Package () { 0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
29 Package () { 0x001EFFFF, 1, 0, eMMC_IRQ },
30 Package () { 0x001EFFFF, 2, 0, SDIO_IRQ },
31 Package () { 0x001EFFFF, 3, 0, SD_IRQ },
32 /* D29: PCI Express Port 9-16 */
33 Package () { 0x001DFFFF, 0, 0, PCIE_9_IRQ },
34 Package () { 0x001DFFFF, 1, 0, PCIE_10_IRQ },
35 Package () { 0x001DFFFF, 2, 0, PCIE_11_IRQ },
36 Package () { 0x001DFFFF, 3, 0, PCIE_12_IRQ },
37 /* D28: PCI Express Port 1-8 */
38 Package () { 0x001CFFFF, 0, 0, PCIE_1_IRQ },
39 Package () { 0x001CFFFF, 1, 0, PCIE_2_IRQ },
40 Package () { 0x001CFFFF, 2, 0, PCIE_3_IRQ },
41 Package () { 0x001CFFFF, 3, 0, PCIE_4_IRQ },
42 /* D25: SerialIo */
43 Package () { 0x0019FFFF, 0, 0, LPSS_UART2_IRQ },
44 Package () { 0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
45 Package () { 0x0019FFFF, 2, 0, LPSS_I2C4_IRQ },
46 /* D22: CSME (HECI, IDE-R, KT redirection */
47 Package () { 0x0016FFFF, 0, 0, HECI_1_IRQ },
48 Package () { 0x0016FFFF, 1, 0, HECI_2_IRQ },
49 Package () { 0x0016FFFF, 2, 0, IDER_IRQ },
50 Package () { 0x0016FFFF, 3, 0, KT_IRQ },
51 /* D21: SerialIo */
52 Package () { 0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
53 Package () { 0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
54 Package () { 0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
55 Package () { 0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
56 /* D20: xHCI, OTG, Thermal, Camera */
57 Package () { 0x0014FFFF, 0, 0, XHCI_IRQ },
58 Package () { 0x0014FFFF, 1, 0, OTG_IRQ },
59 Package () { 0x0014FFFF, 2, 0, THRMAL_IRQ },
60 Package () { 0x0014FFFF, 3, 0, CIO_INTD_IRQ },
61 /* D19: Integrated Sensor Hub */
62 Package () { 0x0013FFFF, 0, 0, ISH_IRQ },
63 /* P.E.G. Root Port D1F0 */
64 Package () { 0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },
65 Package () { 0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },
66 Package () { 0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },
67 Package () { 0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },
68 /* SA IGFX Device */
69 Package () { 0x0002FFFF, 0, 0, IGFX_IRQ },
70 /* SA Thermal Device */
71 Package () { 0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
72 /* SA SkyCam Device */
73 Package () { 0x0005FFFF, 0, 0, SKYCAM_IRQ },
74 /* SA GMM Device */
75 Package () { 0x0008FFFF, 0, 0, GMM_IRQ },
76 })
78 Name (PICN, Package () {
79 /* D31: cAVS, SMBus, GbE, Nothpeak */
80 Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
81 Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
82 Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
83 Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
84 /* D29: PCI Express Port 9-16 */
85 Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
86 Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
87 Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
88 Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
89 /* D28: PCI Express Port 1-8 */
90 Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
91 Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
92 Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
93 Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
94 /* D27: PCI Express Port 17-20 */
95 Package () { 0x001BFFFF, 0, \_SB.PCI0.LNKA, 0 },
96 Package () { 0x001BFFFF, 1, \_SB.PCI0.LNKB, 0 },
97 Package () { 0x001BFFFF, 2, \_SB.PCI0.LNKC, 0 },
98 Package () { 0x001BFFFF, 3, \_SB.PCI0.LNKD, 0 },
99 /* D23 */
100 Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
101 /* D22: CSME (HECI, IDE-R, KT redirection */
102 Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
103 Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
104 Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
105 Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
106 /* D20: xHCI, OTG, Thermal, Camera */
107 Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
108 Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
109 Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
110 Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
111 /* P.E.G. Root Port D1F0 */
112 Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
113 Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
114 Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
115 Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
116 /* SA IGFX Device */
117 Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
118 /* SA Thermal Device */
119 Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
120 /* SA Skycam Device */
121 Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
122 /* SA GMM Device */
123 Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
124 })
126 Method (_PRT)
127 {
128 If (PICM) {
129 Return (^PICP)
130 } Else {
131 Return (^PICN)
132 }
133 }