src/soc/intel/fsp_baytrail/i2c.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2014 Siemens AG
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <device/pci.h>
  17 #include <baytrail/baytrail.h>
  18 #include <baytrail/pci_devs.h>
  19 #include <baytrail/iosf.h>
  20 #include <delay.h>
  21 #include <baytrail/i2c.h>
  22
  23 /* Wait for the transmit FIFO till there is at least one slot empty.
  24  * FIFO stall due to transmit abort will be checked and resolved
  25  */
  26 static int wait_tx_fifo(char *base_adr) {
  27         int i;
  28
  29         if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) {
  30                 /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */
  31                 i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT));
  32                 return I2C_ERR_ABORT |
  33                  (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff);
  34         }
  35
  36         /* Wait here for a free slot in TX-FIFO */
  37         i = I2C_TIMEOUT_US;
  38         while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_TFNF))) {
  39                 udelay(1);
  40                 if (!--i)
  41                         return I2C_ERR_TIMEOUT;
  42         }
  43
  44         return I2C_SUCCESS;
  45 }
  46
  47 /* Wait for the receive FIFO till there is at least one valid entry to read.
  48  * FIFO stall due to transmit abort will be checked and resolved
  49  */
  50 static int wait_rx_fifo(char *base_adr) {
  51         int i;
  52         if (read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff) {
  53                 /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */
  54                 i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT));
  55                 return I2C_ERR_ABORT |
  56                  (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff);
  57         }
  58
  59         /* Wait here for a received entry in RX-FIFO */
  60         i = I2C_TIMEOUT_US;
  61         while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_RFNE))) {
  62                 udelay(1);
  63                 if (!--i)
  64                         return I2C_ERR_TIMEOUT;
  65         }
  66
  67         return I2C_SUCCESS;
  68 }
  69
  70 /* When there will be a fast switch between send and receive, one have
  71  * to wait until the first operation is completely finished
  72  * before starting the second operation
  73  */
  74 static int wait_for_idle(char *base_adr)
  75 {
  76         int i;
  77         volatile int status;
  78
  79         /* For IDLE, increase timeout by ten times */
  80         i = I2C_TIMEOUT_US * 10;
  81         status = *((volatile unsigned int *)(base_adr + I2C_STATUS));
  82         while (((status & I2C_MST_ACTIVITY) || (!(status & I2C_TFE)))) {
  83                 status = *((volatile unsigned int *)(base_adr + I2C_STATUS));
  84                 udelay(1);
  85                 if (!--i)
  86                         return I2C_ERR_TIMEOUT;
  87         }
  88
  89         return I2C_SUCCESS;
  90
  91 }
  92
  93 /** \brief Enables I2C-controller, sets up BAR and timing parameters
  94  * @param   bus Number of the I2C-controller to use (0...6)
  95  * @return  I2C_SUCCESS on success, otherwise error code
  96  */
  97 int i2c_init(unsigned bus)
  98 {
  99         device_t dev;
 100         int base_adr[7] = {I2C0_MEM_BASE, I2C1_MEM_BASE, I2C2_MEM_BASE,
 101                            I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE,
 102                            I2C6_MEM_BASE};
 103         char *base_ptr;
 104         /* Ensure the desired device is valid */
 105         if (bus > ARRAY_SIZE(base_adr)) {
 106                 printk(BIOS_ERR, "I2C: Only I2C controllers 0...6 are available.\n");
 107                 return I2C_ERR;
 108         }
 109
 110         base_ptr = (char*)base_adr[bus];
 111         /* Set the I2C-device the user wants to use */
 112         dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1));
 113
 114         /* Ensure we have the right PCI device */
 115         if ((pci_read_config16(dev, 0x0) != I2C_PCI_VENDOR_ID) ||
 116             (pci_read_config16(dev, 0x2) != (I2C0_PCI_DEV_ID + bus))) {
 117                 printk(BIOS_ERR, "I2C: Controller %d not found!\n", bus);
 118                 return I2C_ERR;
 119         }
 120
 121         /* Set memory base */
 122         pci_write_config32(dev, PCI_BASE_ADDRESS_0, (int)base_ptr);
 123
 124         /* Enable memory space */
 125         pci_write_config32(dev, PCI_COMMAND,
 126                            (pci_read_config32(dev, PCI_COMMAND) | 0x2));
 127
 128         /* Set up some settings of I2C controller */
 129         *((unsigned int *)(base_ptr + I2C_CTRL)) = (I2C_RESTART_EN |
 130                                                   (I2C_STANDARD_MODE << 1) |
 131                                                    I2C_MASTER_ENABLE);
 132         /* Adjust frequency for standard mode to 100 kHz */
 133         /* The counter value can be computed by N=100MHz/2/I2C_CLK */
 134         /* Thus, for 100 kHz I2C_CLK, N is 0x1F4 */
 135         *((unsigned int *)(base_ptr + I2C_SS_SCL_HCNT)) = 0x1f4;
 136         *((unsigned int *)(base_ptr + I2C_SS_SCL_LCNT)) = 0x1f4;
 137         /* For 400 kHz, the counter value is 0x7d */
 138         *((unsigned int *)(base_ptr + I2C_FS_SCL_HCNT)) = 0x7d;
 139         *((unsigned int *)(base_ptr + I2C_FS_SCL_LCNT)) = 0x7d;
 140
 141         /* Enable the I2C controller for operation */
 142         *((unsigned int *)(base_ptr + I2C_ENABLE)) = 0x1;
 143
 144         printk(BIOS_INFO, "I2C: Controller %d enabled.\n", bus);
 145         return I2C_SUCCESS;
 146 }
 147
 148 /** \brief Read bytes over I2C-Bus from a slave. This function tries only one
 149  *         time to transmit data. In case of an error (abort) error code is
 150  *         returned. Retransmission has to be done from caller!
 151  * @param bus  Number of the I2C-controller to use (0...6)
 152  * @param chip 7 Bit of the slave address on I2C bus
 153  * @param addr Address inside slave where to read from
 154  * @param *buf Pointer to the buffer where to store read data
 155  * @param len  Number of bytes to read
 156  * @return     I2C_SUCCESS when read was successful, otherwise error code
 157  */
 158 int i2c_read(unsigned bus, unsigned chip, unsigned addr,
 159                         uint8_t *buf, unsigned len)
 160 {
 161         int i = 0;
 162         char *base_ptr = NULL;
 163         device_t dev;
 164         unsigned int val;
 165         int stat;
 166
 167         /* Get base address of desired I2C-controller */
 168         dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1));
 169         base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 170         if (base_ptr == NULL) {
 171                 printk(BIOS_INFO, "I2C: Invalid Base address\n");
 172                 return I2C_ERR_INVALID_ADR;
 173         }
 174
 175         /* Ensure I2C controller is not active before setting slave address */
 176         stat = wait_for_idle(base_ptr);
 177         if (stat != I2C_SUCCESS)
 178                 return stat;
 179         /* Now we can program the desired slave address and start transfer */
 180         *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff);
 181         /* Send address inside slave to read from */
 182         *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff);
 183
 184         /* For the next byte we need a repeated start condition */
 185         val = I2C_RW_CMD | I2C_RESTART;
 186         /* Now we can read desired amount of data over I2C */
 187         for (i = 0; i < len; i++) {
 188                 /* A read is initiated by writing dummy data to the DATA-register */
 189                 *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val;
 190                 stat = wait_rx_fifo(base_ptr);
 191                 if (stat)
 192                         return stat;
 193                 buf[i] = (*((unsigned int *)(base_ptr + I2C_DATA_CMD))) & 0xff;
 194                 val = I2C_RW_CMD;
 195                 if (i == (len - 2)) {
 196                         /* For the last byte we need a stop condition to be generated */
 197                         val |= I2C_STOP;
 198                 }
 199         }
 200         return I2C_SUCCESS;
 201 }
 202
 203 /** \brief Write bytes over I2C-Bus from a slave. This function tries only one
 204  *         time to transmit data. In case of an error (abort) error code is
 205  *         returned. Retransmission has to be done from caller!
 206  * @param bus  Number of the I2C-controller to use (0...6)
 207  * @param chip 7 Bit of the slave address on I2C bus
 208  * @param addr Address inside slave where to write to
 209  * @param *buf Pointer to the buffer where data to write is stored
 210  * @param len  Number of bytes to write
 211  * @return     I2C_SUCCESS when read was successful, otherwise error code
 212  */
 213 int i2c_write(unsigned bus, unsigned chip, unsigned addr,
 214                         const uint8_t *buf, unsigned len)
 215 {
 216         int i;
 217         char *base_ptr;
 218         device_t dev;
 219         unsigned int val;
 220         int stat;
 221
 222         /* Get base address of desired I2C-controller */
 223         dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1));
 224         base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 225         if (base_ptr == NULL) {
 226                 return I2C_ERR_INVALID_ADR;
 227         }
 228
 229         /* Ensure I2C controller is not active yet */
 230         stat = wait_for_idle(base_ptr);
 231         if (stat) {
 232                 return stat;
 233         }
 234         /* Program slave address to use for this transfer */
 235         *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff);
 236
 237         /* Send address inside slave to write data to */
 238         *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff);
 239
 240         for (i = 0; i < len; i++) {
 241                 val = (unsigned int)(buf[i] & 0xff);    /* Take only 8 bits */
 242                 if (i == (len - 1)) {
 243                         /* For the last byte we need a stop condition */
 244                         val |= I2C_STOP;
 245                 }
 246                 stat = wait_tx_fifo(base_ptr);
 247                 if (stat) {
 248                         return stat;
 249                 }
 250                 *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val;
 251         }
 252         return I2C_SUCCESS;
 253 }