src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
   5  * Copyright (C) 2014 Intel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef CHIPSET_FSP_UTIL_H
  18 #define CHIPSET_FSP_UTIL_H
  19
  20 #include <fsp.h>
  21 #include <fsptypes.h>
  22 #include <fspfv.h>
  23 #include <fspffs.h>
  24 #include <fspapi.h>
  25 #include <fspplatform.h>
  26 #include <fspinfoheader.h>
  27 #include <fsphob.h>
  28 #include <fspvpd.h>
  29 #include <azalia.h>
  30
  31 #define FSP_INFO_HEADER_GUID \
  32   { \
  33   0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \
  34   }
  35
  36 /*
  37  * The FSP Image ID is different for each platform's FSP and
  38  * can be used to verify that the right FSP binary is loaded.
  39  * For the Bay Trail FSP, the Image Id is "VLYVIEW0".
  40  */
  41 #define FSP_IMAGE_ID_DWORD0 0x56594C56  /* 'VLYV' */
  42 #define FSP_IMAGE_ID_DWORD1 0x30574549  /* 'IEW0' */
  43
  44 /* Revision of the FSP binary */
  45 #define FSP_GOLD3_REV_ID    0x00000303
  46
  47 #define NO_DECREMENT_FOR_DEFAULT        0
  48 #define DECREMENT_FOR_DEFAULT           1
  49
  50 #define UPD_MEMDOWN_CHECK(member, adjust) \
  51         if (config->member != UPD_DEFAULT) { \
  52                 UpdData->PcdMemoryParameters.member = config->member - adjust; \
  53         }
  54
  55 #endif /* CHIPSET_FSP_UTIL_H */