src/soc/intel/fsp_baytrail/baytrail/pcie.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Google, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef _BAYTRAIL_PCIE_H_
  17 #define _BAYTRAIL_PCIE_H_
  18
  19 /* PCIe root port config space registers. */
  20 #define XCAP                    0x40
  21 # define SI                     (1 << 24)
  22 #define DCAP                    0x44
  23 # define MPS_MASK               0x7
  24 #define DCTL_DSTS               0x48
  25 # define URE                    (1 << 3)
  26 # define FEE                    (1 << 2)
  27 # define NFE                    (1 << 1)
  28 # define CEE                    (1 << 0)
  29 #define LCAP                    0x4c
  30 # define L1EXIT_SHIFT           15
  31 # define L1EXIT_MASK            (0x7 << L1EXIT_SHIFT)
  32 #define LCTL                    0x50
  33 # define CCC                    (1 << 6)
  34 # define RL                     (1 << 5)
  35 # define LD                     (1 << 4)
  36 #define LSTS                    0x52
  37 #define SLCAP                   0x54
  38 # define SLN_SHIFT              19
  39 # define SLS_SHIFT              15
  40 # define SLV_SHIFT              7
  41 # define HPC                    (1 << 6)
  42 # define HPS                    (1 << 5)
  43 #define SLCTL_SLSTS             0x58
  44 # define PDS                    (1 << 22)
  45 #define DCAP2                   0x64
  46 # define OBFFS                  (0x3 << 18)
  47 # define LTRMS                  (1 << 11)
  48 #define DSTS2                   0x68
  49 # define OBFFEN                 (3 << 13)
  50 # define LTRME                  (1 << 10)
  51 # define CTD                    (1 <<  4)
  52 #define CHCFG                   0xd0
  53 # define UPSD                   (1 << 24)
  54 # define UNRS                   (1 << 15)
  55 # define UPRS                   (1 << 14)
  56 #define MPC2                    0xd4
  57 # define IPF                    (1 << 11)
  58 # define LSTP                   (1 <<  6)
  59 # define EOIFD                  (1 <<  1)
  60 #define MPC                     0xd8
  61 # define CCEL_SHIFT             15
  62 # define CCEL_MASK              (0x7 << CCEL_SHIFT)
  63 #define RPPGEN                  0xe0
  64 # define RPSCGEN                (1 << 15)
  65 # define LCLKREQEN              (1 << 13)
  66 # define BBCLKREQEN             (1 << 12)
  67 # define SRDLCGEN               (1 << 11)
  68 # define SRDBCGEN               (1 << 10)
  69 # define RPDLCGEN               (1 << 9)
  70 # define RPDBCGEN               (1 << 8)
  71 #define PWRCTL                  0xe8
  72 # define RPL1SQPOL              (1 << 1)
  73 # define RPDTSQPOL              (1 << 0)
  74 #define PHYCTL2_IOSFBCTL        0xf4
  75 # define PLL_OFF_EN             (1 << 8)
  76 # define TDFT                   (3 << 14)
  77 # define TXCFGCHWAIT            (3 << 12)
  78 # define SIID                   (3 << 26)
  79 #define STRPFUSECFG             0xfc
  80 # define LANECFG_SHIFT          14
  81 # define LANECFG_MASK           (0x3 << LANECFG_SHIFT)
  82 #define AERCH                   0x100
  83 #define NFTS                    0x314
  84 #define L0SC                    0x318
  85 #define CFG2                    0x320
  86 # define CSREN                  (1 << 22)
  87 # define LATGC_SHIFT            6
  88 # define LATGC_MASK             (0x7 << LATGC_SHIFT)
  89 #define PCIEDBG                 0x324
  90 # define SPCE                   (1 << 5)
  91 #define PCIESTS1                0x328
  92 #define PCIEALC                 0x338
  93 #define RTP                     0x33c
  94 #define PHYCTL4                 0x408
  95 # define SQDIS                  (1 << 27)
  96
  97
  98 #endif /* _BAYTRAIL_PCIE_H_ */