src/soc/intel/fsp_baytrail/baytrail/iomap.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef _BAYTRAIL_IOMAP_H_
  17 #define _BAYTRAIL_IOMAP_H_
  18
  19
  20 /*
  21  * Memory Mapped IO bases.
  22  */
  23
  24 /* PCI Configuration Space */
  25 #define MCFG_BASE_ADDRESS               CONFIG_MMCONF_BASE_ADDRESS
  26 #define MCFG_BASE_SIZE                  0x10000000
  27
  28 /* Transactions in this range will abort */
  29 #define ABORT_BASE_ADDRESS              0xfeb00000
  30 #define ABORT_BASE_SIZE                 0x00100000
  31
  32 /* Power Management Controller */
  33 #define PMC_BASE_ADDRESS                0xfed03000
  34 #define PMC_BASE_SIZE                   0x400
  35
  36 /* IO Memory */
  37 #define IO_BASE_ADDRESS                 0xfed0c000
  38 #define  IO_BASE_OFFSET_GPSCORE         0x0000
  39 #define  IO_BASE_OFFSET_GPNCORE         0x1000
  40 #define  IO_BASE_OFFSET_GPSSUS          0x2000
  41 #define IO_BASE_SIZE                    0x4000
  42
  43 /* Intel Legacy Block */
  44 #define ILB_BASE_ADDRESS                0xfed08000
  45 #define ILB_BASE_SIZE                   0x400
  46
  47 /* SPI Bus */
  48 #define SPI_BASE_ADDRESS                0xfed01000
  49 #define SPI_BASE_SIZE                   0x400
  50
  51 /* MODPHY */
  52 #define MPHY_BASE_ADDRESS               0xfef00000
  53 #define MPHY_BASE_SIZE                  0x100000
  54
  55 /* Power Management Unit */
  56 #define PUNIT_BASE_ADDRESS              0xfed05000
  57 #define PUNIT_BASE_SIZE                 0x800
  58
  59 /* Root Complex Base Address */
  60 #define RCBA_BASE_ADDRESS               0xfed1c000
  61 #define RCBA_BASE_SIZE                  0x400
  62
  63 /* High Performance Event Timer */
  64 #define HPET_BASE_ADDRESS               0xfed00000
  65 #define HPET_BASE_SIZE                  0x400
  66
  67 /* Temporary Base Address */
  68 #define TEMP_BASE_ADDRESS               0xfd000000
  69
  70 /*
  71  * IO Port bases.
  72  */
  73 #define ACPI_BASE_ADDRESS               0x0400
  74 #define ACPI_BASE_SIZE                  0x80
  75
  76 #define GPIO_BASE_ADDRESS               0x0500
  77 #define GPIO_BASE_SIZE                  0x100
  78
  79 #define SMBUS_BASE_ADDRESS              0xefa0
  80
  81 #ifndef __ACPI__
  82 /* Read Top of Low Memory (BMBOUND) */
  83 uint32_t nc_read_top_of_low_memory(void);
  84 #endif
  85
  86 #endif /* _BAYTRAIL_IOMAP_H_ */