src/soc/intel/fsp_baytrail/baytrail/baytrail.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 coresystems GmbH
   5  * Copyright (C) 2011 Google Inc.
   6  * Copyright (C) 2013 Sage Electronic Engineering, LLC.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #ifndef __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__
  19 #define __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__
  20
  21 #define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS
  22 #define CPU_MICROCODE_CBFS_LEN 0x26000
  23
  24 /* Southbridge internal device IO BARs (Set to match FSP settings) */
  25 #define SMBUS_IO_BASE           0xefa0
  26 #define SMBUS_SLAVE_ADDR        0x24
  27 #define DEFAULT_GPIOBASE        0x0500
  28 #define DEFAULT_ABASE           0x0400
  29
  30 /* Southbridge internal device MEM BARs (Set to match FSP settings) */
  31 #define DEFAULT_IBASE           0xfed08000
  32 #define DEFAULT_PBASE           0xfed03000
  33 #ifndef __ACPI__
  34 #define DEFAULT_RCBA            ((u8 *)0xfed1c000)
  35 #else
  36 #define DEFAULT_RCBA            0xfed1c000
  37 #endif
  38 /* Everything below this line is ignored in the DSDT */
  39 #ifndef __ACPI__
  40
  41 /* Device 0:0.0 PCI configuration space (Host Bridge) */
  42
  43 /* SOC types */
  44 #define SOC_TYPE_BAYTRAIL       0x0F1C
  45
  46 #ifndef __ASSEMBLER__
  47 static inline void barrier(void) { asm("" ::: "memory"); }
  48
  49 #define SKPAD 0xFC
  50
  51 int bridge_silicon_revision(void);
  52 void rangeley_early_initialization(void);
  53
  54 #ifndef __PRE_RAM__
  55 /* soc.c */
  56 int soc_silicon_revision(void);
  57 int soc_silicon_type(void);
  58 int soc_silicon_supported(int type, int rev);
  59 void soc_enable(device_t dev);
  60
  61 /* debugging functions */
  62 void print_pci_devices(void);
  63 void dump_pci_device(unsigned dev);
  64 void dump_pci_devices(void);
  65 void dump_spd_registers(void);
  66 void dump_mem(unsigned start, unsigned end);
  67 void report_platform_info(void);
  68
  69 #endif  /* __PRE_RAM__ */
  70 #endif  /* __ASSEMBLER__ */
  71
  72 #endif  /* __ACPI__ */
  73 #endif