src/soc/intel/fsp_baytrail/acpi/southcluster.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <soc/intel/fsp_baytrail/baytrail/iomap.h>
  18 #include <soc/intel/fsp_baytrail/baytrail/irq.h>
  19 #include "../baytrail/baytrail.h"
  20
  21 Scope(\)
  22 {
  23         // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
  24
  25         OperationRegion(IO_T, SystemIO, 0x800, 0x10)
  26         Field(IO_T, ByteAcc, NoLock, Preserve)
  27         {
  28                 Offset(0x8),
  29                 TRP0, 8         // IO-Trap at 0x808
  30         }
  31
  32         // Intel Legacy Block
  33         OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
  34         Field (ILBS, AnyAcc, NoLock, Preserve)
  35         {
  36                 Offset (0x8),
  37                 PRTA, 8,
  38                 PRTB, 8,
  39                 PRTC, 8,
  40                 PRTD, 8,
  41                 PRTE, 8,
  42                 PRTF, 8,
  43                 PRTG, 8,
  44                 PRTH, 8,
  45         }
  46 }
  47
  48 Name(_HID,EISAID("PNP0A08"))    // PCIe
  49 Name(_CID,EISAID("PNP0A03"))    // PCI
  50
  51 Name(_ADR, 0)
  52 Name(_BBN, 0)
  53
  54 Name (MCRS, ResourceTemplate()
  55 {
  56         // Bus Numbers
  57         WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
  58                         0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
  59
  60         // IO Region 0
  61         DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
  62                         0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
  63
  64         // PCI Config Space
  65         Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
  66
  67         // IO Region 1
  68         DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
  69                         0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
  70
  71         // VGA memory (0xa0000-0xbffff)
  72         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
  73                         Cacheable, ReadWrite,
  74                         0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
  75                         0x00020000,,, ASEG)
  76
  77         // OPROM reserved (0xc0000-0xc3fff)
  78         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
  79                         Cacheable, ReadWrite,
  80                         0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
  81                         0x00004000,,, OPR0)
  82
  83         // OPROM reserved (0xc4000-0xc7fff)
  84         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
  85                         Cacheable, ReadWrite,
  86                         0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
  87                         0x00004000,,, OPR1)
  88
  89         // OPROM reserved (0xc8000-0xcbfff)
  90         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
  91                         Cacheable, ReadWrite,
  92                         0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
  93                         0x00004000,,, OPR2)
  94
  95         // OPROM reserved (0xcc000-0xcffff)
  96         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
  97                         Cacheable, ReadWrite,
  98                         0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
  99                         0x00004000,,, OPR3)
 100
 101         // OPROM reserved (0xd0000-0xd3fff)
 102         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 103                         Cacheable, ReadWrite,
 104                         0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
 105                         0x00004000,,, OPR4)
 106
 107         // OPROM reserved (0xd4000-0xd7fff)
 108         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 109                         Cacheable, ReadWrite,
 110                         0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
 111                         0x00004000,,, OPR5)
 112
 113         // OPROM reserved (0xd8000-0xdbfff)
 114         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 115                         Cacheable, ReadWrite,
 116                         0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
 117                         0x00004000,,, OPR6)
 118
 119         // OPROM reserved (0xdc000-0xdffff)
 120         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 121                         Cacheable, ReadWrite,
 122                         0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
 123                         0x00004000,,, OPR7)
 124
 125         // BIOS Extension (0xe0000-0xe3fff)
 126         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 127                         Cacheable, ReadWrite,
 128                         0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
 129                         0x00004000,,, ESG0)
 130
 131         // BIOS Extension (0xe4000-0xe7fff)
 132         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 133                         Cacheable, ReadWrite,
 134                         0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
 135                         0x00004000,,, ESG1)
 136
 137         // BIOS Extension (0xe8000-0xebfff)
 138         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 139                         Cacheable, ReadWrite,
 140                         0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
 141                         0x00004000,,, ESG2)
 142
 143         // BIOS Extension (0xec000-0xeffff)
 144         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 145                         Cacheable, ReadWrite,
 146                         0x00000000, 0x000ec000, 0x000effff, 0x00000000,
 147                         0x00004000,,, ESG3)
 148
 149         // System BIOS (0xf0000-0xfffff)
 150         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 151                         Cacheable, ReadWrite,
 152                         0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 153                         0x00010000,,, FSEG)
 154
 155         // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
 156         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 157                         Cacheable, ReadWrite,
 158                         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 159                         0x00000000,,, PMEM)
 160
 161         // TPM Area (0xfed40000-0xfed44fff)
 162         DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 163                         Cacheable, ReadWrite,
 164                         0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
 165                         0x00005000,,, TPMR)
 166 })
 167
 168 Method (_CRS, 0, Serialized)
 169 {
 170         // Update PCI resource area
 171         CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
 172         CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
 173         CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
 174
 175         // TOLM is BMBOUND accessible from IOSF so is saved in NVS
 176         Store (\TOLM, PMIN)
 177         Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
 178         Add (Subtract (PMAX, PMIN), 1, PLEN)
 179
 180         Return (MCRS)
 181 }
 182
 183 /* Device Resource Consumption */
 184 Device (PDRC)
 185 {
 186         Name (_HID, EISAID("PNP0C02"))
 187         Name (_UID, 1)
 188
 189         Name (PDRS, ResourceTemplate() {
 190                 Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
 191                 Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
 192                 Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
 193                 Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
 194                 Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
 195                 Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
 196                 Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
 197                 Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
 198         })
 199
 200         // Current Resource Settings
 201         Method (_CRS, 0, Serialized)
 202         {
 203                 Return(PDRS)
 204         }
 205 }
 206
 207 Method (_OSC, 4)
 208 {
 209         /* Check for proper GUID */
 210         If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
 211         {
 212                 /* Let OS control everything */
 213                 Return (Arg3)
 214         }
 215         Else
 216         {
 217                 /* Unrecognized UUID */
 218                 CreateDWordField (Arg3, 0, CDW1)
 219                 Or (CDW1, 4, CDW1)
 220                 Return (Arg3)
 221         }
 222 }
 223
 224 /* IOSF MBI Interface for kernel access */
 225 Device (IOSF)
 226 {
 227         Name (_HID, "INT33BD")
 228         Name (_CID, "INT33BD")
 229         Name (_UID, 1)
 230
 231         Name (RBUF, ResourceTemplate ()
 232         {
 233                 /* MCR / MDR / MCRX */
 234                 Memory32Fixed (ReadWrite, 0, 12, RBAR)
 235         })
 236
 237         Method (_CRS)
 238         {
 239                 CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
 240                 Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS)
 241                 Return (^RBUF)
 242         }
 243 }
 244
 245 // LPC Bridge 0:1f.0
 246 #include "lpc.asl"
 247
 248 #if INCLUDE_EHCI
 249 // USB EHCI 0:1d.0
 250 #include "usb.asl"
 251 #endif
 252
 253 #if INCLUDE_XHCI
 254 // USB XHCI 0:14.0
 255 #include "xhci.asl"
 256 #endif
 257
 258 // IRQ routing for each PCI device
 259 #include "irqroute.asl"
 260
 261 Scope (\_SB)
 262 {
 263         // GPIO Devices
 264         #include "gpio.asl"
 265
 266 #if INCLUDE_LPSS
 267         // LPSS Devices
 268         #include "lpss.asl"
 269 #endif
 270
 271 #if INCLUDE_SCC
 272         // SCC Devices
 273         #include "scc.asl"
 274 #endif
 275
 276 #if INCLUDE_LPE
 277         // LPE Device
 278         #include "lpe.asl"
 279 #endif
 280 }