src/soc/intel/broadwell/romstage/smbus.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2014 Google Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include <console/console.h>
  19 #include <device/pci_ids.h>
  20 #include <device/pci_def.h>
  21 #include <reg_script.h>
  22 #include <soc/iomap.h>
  23 #include <soc/pci_devs.h>
  24 #include <soc/smbus.h>
  25 #include <soc/romstage.h>
  26
  27 static const struct reg_script smbus_init_script[] = {
  28         /* Set SMBUS I/O base address */
  29         REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1),
  30         /* Set SMBUS enable */
  31         REG_PCI_WRITE8(HOSTC, HST_EN),
  32         /* Enable I/O access */
  33         REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO),
  34         /* Disable interrupts */
  35         REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
  36         /* Clear errors */
  37         REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
  38         /* Indicate the end of this array by REG_SCRIPT_END */
  39         REG_SCRIPT_END,
  40 };
  41
  42 void enable_smbus(void)
  43 {
  44         reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
  45 }
  46
  47 int smbus_read_byte(unsigned device, unsigned address)
  48 {
  49         return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address);
  50 }