src/soc/intel/broadwell/acpi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 coresystems GmbH
   5  * Copyright (C) 2014 Google Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/acpi.h>
  18 #include <arch/acpigen.h>
  19 #include <arch/io.h>
  20 #include <arch/smp/mpspec.h>
  21 #include <cbmem.h>
  22 #include <console/console.h>
  23 #include <cpu/x86/smm.h>
  24 #include <console/console.h>
  25 #include <types.h>
  26 #include <string.h>
  27 #include <arch/cpu.h>
  28 #include <cpu/x86/msr.h>
  29 #include <cpu/x86/tsc.h>
  30 #include <cpu/intel/turbo.h>
  31 #include <ec/google/chromeec/ec.h>
  32 #include <vendorcode/google/chromeos/gnvs.h>
  33 #include <soc/acpi.h>
  34 #include <soc/cpu.h>
  35 #include <soc/iomap.h>
  36 #include <soc/lpc.h>
  37 #include <soc/msr.h>
  38 #include <soc/pci_devs.h>
  39 #include <soc/pm.h>
  40 #include <soc/intel/broadwell/chip.h>
  41
  42 /*
  43  * List of supported C-states in this processor. Only the ULT parts support C8,
  44  * C9, and C10.
  45  */
  46 enum {
  47         C_STATE_C0,             /* 0 */
  48         C_STATE_C1,             /* 1 */
  49         C_STATE_C1E,            /* 2 */
  50         C_STATE_C3,             /* 3 */
  51         C_STATE_C6_SHORT_LAT,   /* 4 */
  52         C_STATE_C6_LONG_LAT,    /* 5 */
  53         C_STATE_C7_SHORT_LAT,   /* 6 */
  54         C_STATE_C7_LONG_LAT,    /* 7 */
  55         C_STATE_C7S_SHORT_LAT,  /* 8 */
  56         C_STATE_C7S_LONG_LAT,   /* 9 */
  57         C_STATE_C8,             /* 10 */
  58         C_STATE_C9,             /* 11 */
  59         C_STATE_C10,            /* 12 */
  60         NUM_C_STATES
  61 };
  62
  63 #define MWAIT_RES(state, sub_state)                         \
  64         {                                                   \
  65                 .addrl = (((state) << 4) | (sub_state)),    \
  66                 .space_id = ACPI_ADDRESS_SPACE_FIXED,       \
  67                 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,    \
  68                 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,    \
  69                 .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
  70         }
  71
  72 static acpi_cstate_t cstate_map[NUM_C_STATES] = {
  73         [C_STATE_C0] = { },
  74         [C_STATE_C1] = {
  75                 .latency = 0,
  76                 .power = 1000,
  77                 .resource = MWAIT_RES(0,0),
  78         },
  79         [C_STATE_C1E] = {
  80                 .latency = 0,
  81                 .power = 1000,
  82                 .resource = MWAIT_RES(0,1),
  83         },
  84         [C_STATE_C3] = {
  85                 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
  86                 .power = 900,
  87                 .resource = MWAIT_RES(1, 0),
  88         },
  89         [C_STATE_C6_SHORT_LAT] = {
  90                 .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
  91                 .power = 800,
  92                 .resource = MWAIT_RES(2, 0),
  93         },
  94         [C_STATE_C6_LONG_LAT] = {
  95                 .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
  96                 .power = 800,
  97                 .resource = MWAIT_RES(2, 1),
  98         },
  99         [C_STATE_C7_SHORT_LAT] = {
 100                 .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
 101                 .power = 700,
 102                 .resource = MWAIT_RES(3, 0),
 103         },
 104         [C_STATE_C7_LONG_LAT] = {
 105                 .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
 106                 .power = 700,
 107                 .resource = MWAIT_RES(3, 1),
 108         },
 109         [C_STATE_C7S_SHORT_LAT] = {
 110                 .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
 111                 .power = 700,
 112                 .resource = MWAIT_RES(3, 2),
 113         },
 114         [C_STATE_C7S_LONG_LAT] = {
 115                 .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
 116                 .power = 700,
 117                 .resource = MWAIT_RES(3, 3),
 118         },
 119         [C_STATE_C8] = {
 120                 .latency = C_STATE_LATENCY_FROM_LAT_REG(3),
 121                 .power = 600,
 122                 .resource = MWAIT_RES(4, 0),
 123         },
 124         [C_STATE_C9] = {
 125                 .latency = C_STATE_LATENCY_FROM_LAT_REG(4),
 126                 .power = 500,
 127                 .resource = MWAIT_RES(5, 0),
 128         },
 129         [C_STATE_C10] = {
 130                 .latency = C_STATE_LATENCY_FROM_LAT_REG(5),
 131                 .power = 400,
 132                 .resource = MWAIT_RES(6, 0),
 133         },
 134 };
 135
 136 static int cstate_set_s0ix[3] = {
 137         C_STATE_C1E,
 138         C_STATE_C7S_LONG_LAT,
 139         C_STATE_C10
 140 };
 141
 142 static int cstate_set_non_s0ix[3] = {
 143         C_STATE_C1E,
 144         C_STATE_C3,
 145         C_STATE_C7S_LONG_LAT
 146 };
 147
 148 static int get_cores_per_package(void)
 149 {
 150         struct cpuinfo_x86 c;
 151         struct cpuid_result result;
 152         int cores = 1;
 153
 154         get_fms(&c, cpuid_eax(1));
 155         if (c.x86 != 6)
 156                 return 1;
 157
 158         result = cpuid_ext(0xb, 1);
 159         cores = result.ebx & 0xff;
 160
 161         return cores;
 162 }
 163
 164 void acpi_init_gnvs(global_nvs_t *gnvs)
 165 {
 166         /* Set unknown wake source */
 167         gnvs->pm1i = -1;
 168
 169         /* CPU core count */
 170         gnvs->pcnt = dev_count_cpu();
 171
 172 #if CONFIG_CONSOLE_CBMEM
 173         /* Update the mem console pointer. */
 174         gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 175 #endif
 176
 177 #if CONFIG_CHROMEOS
 178         /* Initialize Verified Boot data */
 179         chromeos_init_vboot(&(gnvs->chromeos));
 180 #if CONFIG_EC_GOOGLE_CHROMEEC
 181         gnvs->chromeos.vbt2 = google_ec_running_ro() ?
 182                 ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
 183 #endif
 184         gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
 185 #endif
 186 }
 187
 188 void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 189 {
 190         acpi_header_t *header = &(hpet->header);
 191         acpi_addr_t *addr = &(hpet->addr);
 192
 193         memset((void *) hpet, 0, sizeof(acpi_hpet_t));
 194
 195         /* fill out header fields */
 196         memcpy(header->signature, "HPET", 4);
 197         memcpy(header->oem_id, OEM_ID, 6);
 198         memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 199         memcpy(header->asl_compiler_id, ASLC, 4);
 200
 201         header->length = sizeof(acpi_hpet_t);
 202         header->revision = 1;
 203
 204         /* fill out HPET address */
 205         addr->space_id = 0;     /* Memory */
 206         addr->bit_width = 64;
 207         addr->bit_offset = 0;
 208         addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff;
 209         addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32;
 210
 211         hpet->id = 0x8086a201;  /* Intel */
 212         hpet->number = 0x00;
 213         hpet->min_tick = 0x0080;
 214
 215         header->checksum =
 216             acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
 217 }
 218
 219 unsigned long acpi_fill_mcfg(unsigned long current)
 220 {
 221         current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
 222                                              MCFG_BASE_ADDRESS, 0, 0, 255);
 223         return current;
 224 }
 225
 226 void acpi_fill_in_fadt(acpi_fadt_t *fadt)
 227 {
 228         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 229
 230         fadt->sci_int = acpi_sci_irq();
 231         fadt->smi_cmd = APM_CNT;
 232         fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
 233         fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 234         fadt->s4bios_req = 0x0;
 235         fadt->pstate_cnt = 0;
 236
 237         fadt->pm1a_evt_blk = pmbase + PM1_STS;
 238         fadt->pm1b_evt_blk = 0x0;
 239         fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
 240         fadt->pm1b_cnt_blk = 0x0;
 241         fadt->pm2_cnt_blk = pmbase + PM2_CNT;
 242         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 243         fadt->gpe0_blk = pmbase + GPE0_STS(0);
 244         fadt->gpe1_blk = 0;
 245
 246         fadt->pm1_evt_len = 4;
 247         fadt->pm1_cnt_len = 2;
 248         fadt->pm2_cnt_len = 1;
 249         fadt->pm_tmr_len = 4;
 250         fadt->gpe0_blk_len = 32;
 251         fadt->gpe1_blk_len = 0;
 252         fadt->gpe1_base = 0;
 253         fadt->cst_cnt = 0;
 254         fadt->p_lvl2_lat = 1;
 255         fadt->p_lvl3_lat = 87;
 256         fadt->flush_size = 1024;
 257         fadt->flush_stride = 16;
 258         fadt->duty_offset = 1;
 259         fadt->duty_width = 0;
 260         fadt->day_alrm = 0xd;
 261         fadt->mon_alrm = 0x00;
 262         fadt->century = 0x00;
 263         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
 264
 265         fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
 266                         ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
 267                         ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
 268                         ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
 269
 270         fadt->reset_reg.space_id = 1;
 271         fadt->reset_reg.bit_width = 8;
 272         fadt->reset_reg.bit_offset = 0;
 273         fadt->reset_reg.resv = 0;
 274         fadt->reset_reg.addrl = 0xcf9;
 275         fadt->reset_reg.addrh = 0;
 276         fadt->reset_value = 6;
 277
 278         fadt->x_pm1a_evt_blk.space_id = 1;
 279         fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
 280         fadt->x_pm1a_evt_blk.bit_offset = 0;
 281         fadt->x_pm1a_evt_blk.resv = 0;
 282         fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
 283         fadt->x_pm1a_evt_blk.addrh = 0x0;
 284
 285         fadt->x_pm1b_evt_blk.space_id = 1;
 286         fadt->x_pm1b_evt_blk.bit_width = 0;
 287         fadt->x_pm1b_evt_blk.bit_offset = 0;
 288         fadt->x_pm1b_evt_blk.resv = 0;
 289         fadt->x_pm1b_evt_blk.addrl = 0x0;
 290         fadt->x_pm1b_evt_blk.addrh = 0x0;
 291
 292         fadt->x_pm1a_cnt_blk.space_id = 1;
 293         fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
 294         fadt->x_pm1a_cnt_blk.bit_offset = 0;
 295         fadt->x_pm1a_cnt_blk.resv = 0;
 296         fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
 297         fadt->x_pm1a_cnt_blk.addrh = 0x0;
 298
 299         fadt->x_pm1b_cnt_blk.space_id = 1;
 300         fadt->x_pm1b_cnt_blk.bit_width = 0;
 301         fadt->x_pm1b_cnt_blk.bit_offset = 0;
 302         fadt->x_pm1b_cnt_blk.resv = 0;
 303         fadt->x_pm1b_cnt_blk.addrl = 0x0;
 304         fadt->x_pm1b_cnt_blk.addrh = 0x0;
 305
 306         fadt->x_pm2_cnt_blk.space_id = 1;
 307         fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
 308         fadt->x_pm2_cnt_blk.bit_offset = 0;
 309         fadt->x_pm2_cnt_blk.resv = 0;
 310         fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
 311         fadt->x_pm2_cnt_blk.addrh = 0x0;
 312
 313         fadt->x_pm_tmr_blk.space_id = 1;
 314         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 315         fadt->x_pm_tmr_blk.bit_offset = 0;
 316         fadt->x_pm_tmr_blk.resv = 0;
 317         fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
 318         fadt->x_pm_tmr_blk.addrh = 0x0;
 319
 320         fadt->x_gpe0_blk.space_id = 0;
 321         fadt->x_gpe0_blk.bit_width = 0;
 322         fadt->x_gpe0_blk.bit_offset = 0;
 323         fadt->x_gpe0_blk.resv = 0;
 324         fadt->x_gpe0_blk.addrl = 0;
 325         fadt->x_gpe0_blk.addrh = 0;
 326
 327         fadt->x_gpe1_blk.space_id = 1;
 328         fadt->x_gpe1_blk.bit_width = 0;
 329         fadt->x_gpe1_blk.bit_offset = 0;
 330         fadt->x_gpe1_blk.resv = 0;
 331         fadt->x_gpe1_blk.addrl = 0x0;
 332         fadt->x_gpe1_blk.addrh = 0x0;
 333 }
 334
 335 static acpi_tstate_t tss_table_fine[] = {
 336         { 100, 1000, 0, 0x00, 0 },
 337         { 94, 940, 0, 0x1f, 0 },
 338         { 88, 880, 0, 0x1e, 0 },
 339         { 82, 820, 0, 0x1d, 0 },
 340         { 75, 760, 0, 0x1c, 0 },
 341         { 69, 700, 0, 0x1b, 0 },
 342         { 63, 640, 0, 0x1a, 0 },
 343         { 57, 580, 0, 0x19, 0 },
 344         { 50, 520, 0, 0x18, 0 },
 345         { 44, 460, 0, 0x17, 0 },
 346         { 38, 400, 0, 0x16, 0 },
 347         { 32, 340, 0, 0x15, 0 },
 348         { 25, 280, 0, 0x14, 0 },
 349         { 19, 220, 0, 0x13, 0 },
 350         { 13, 160, 0, 0x12, 0 },
 351 };
 352
 353 static acpi_tstate_t tss_table_coarse[] = {
 354         { 100, 1000, 0, 0x00, 0 },
 355         { 88, 875, 0, 0x1f, 0 },
 356         { 75, 750, 0, 0x1e, 0 },
 357         { 63, 625, 0, 0x1d, 0 },
 358         { 50, 500, 0, 0x1c, 0 },
 359         { 38, 375, 0, 0x1b, 0 },
 360         { 25, 250, 0, 0x1a, 0 },
 361         { 13, 125, 0, 0x19, 0 },
 362 };
 363
 364 static void generate_T_state_entries(int core, int cores_per_package)
 365 {
 366         /* Indicate SW_ALL coordination for T-states */
 367         acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
 368
 369         /* Indicate FFixedHW so OS will use MSR */
 370         acpigen_write_empty_PTC();
 371
 372         /* Set a T-state limit that can be modified in NVS */
 373         acpigen_write_TPC("\\TLVL");
 374
 375         /*
 376          * CPUID.(EAX=6):EAX[5] indicates support
 377          * for extended throttle levels.
 378          */
 379         if (cpuid_eax(6) & (1 << 5))
 380                 acpigen_write_TSS_package(
 381                         ARRAY_SIZE(tss_table_fine), tss_table_fine);
 382         else
 383                 acpigen_write_TSS_package(
 384                         ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
 385 }
 386
 387 static void generate_C_state_entries(void)
 388 {
 389         device_t dev = SA_DEV_ROOT;
 390         config_t *config = dev->chip_info;
 391         acpi_cstate_t map[3];
 392         int *set;
 393         int i;
 394
 395         if (config->s0ix_enable)
 396                 set = cstate_set_s0ix;
 397         else
 398                 set = cstate_set_non_s0ix;
 399
 400         for (i = 0; i < 3; i++) {
 401                 memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
 402                 map[i].ctype = i + 1;
 403         }
 404
 405         /* Generate C-state tables */
 406         acpigen_write_CST_package(map, ARRAY_SIZE(map));
 407 }
 408
 409 static int calculate_power(int tdp, int p1_ratio, int ratio)
 410 {
 411         u32 m;
 412         u32 power;
 413
 414         /*
 415          * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
 416          *
 417          * Power = (ratio / p1_ratio) * m * tdp
 418          */
 419
 420         m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
 421         m = (m * m) / 1000;
 422
 423         power = ((ratio * 100000 / p1_ratio) / 100);
 424         power *= (m / 100) * (tdp / 1000);
 425         power /= 1000;
 426
 427         return (int)power;
 428 }
 429
 430 static void generate_P_state_entries(int core, int cores_per_package)
 431 {
 432         int ratio_min, ratio_max, ratio_turbo, ratio_step;
 433         int coord_type, power_max, power_unit, num_entries;
 434         int ratio, power, clock, clock_max;
 435         msr_t msr;
 436
 437         /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
 438         msr = rdmsr(MSR_MISC_PWR_MGMT);
 439         if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
 440                 coord_type = SW_ANY;
 441         else
 442                 coord_type = HW_ALL;
 443
 444         /* Get bus ratio limits and calculate clock speeds */
 445         msr = rdmsr(MSR_PLATFORM_INFO);
 446         ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
 447
 448         /* Determine if this CPU has configurable TDP */
 449         if (cpu_config_tdp_levels()) {
 450                 /* Set max ratio to nominal TDP ratio */
 451                 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
 452                 ratio_max = msr.lo & 0xff;
 453         } else {
 454                 /* Max Non-Turbo Ratio */
 455                 ratio_max = (msr.lo >> 8) & 0xff;
 456         }
 457         clock_max = ratio_max * CPU_BCLK;
 458
 459         /* Calculate CPU TDP in mW */
 460         msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
 461         power_unit = 2 << ((msr.lo & 0xf) - 1);
 462         msr = rdmsr(MSR_PKG_POWER_SKU);
 463         power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
 464
 465         /* Write _PCT indicating use of FFixedHW */
 466         acpigen_write_empty_PCT();
 467
 468         /* Write _PPC with no limit on supported P-state */
 469         acpigen_write_PPC_NVS();
 470
 471         /* Write PSD indicating configured coordination type */
 472         acpigen_write_PSD_package(core, 1, coord_type);
 473
 474         /* Add P-state entries in _PSS table */
 475         acpigen_write_name("_PSS");
 476
 477         /* Determine ratio points */
 478         ratio_step = PSS_RATIO_STEP;
 479         num_entries = (ratio_max - ratio_min) / ratio_step;
 480         while (num_entries > PSS_MAX_ENTRIES-1) {
 481                 ratio_step <<= 1;
 482                 num_entries >>= 1;
 483         }
 484
 485         /* P[T] is Turbo state if enabled */
 486         if (get_turbo_state() == TURBO_ENABLED) {
 487                 /* _PSS package count including Turbo */
 488                 acpigen_write_package(num_entries + 2);
 489
 490                 msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
 491                 ratio_turbo = msr.lo & 0xff;
 492
 493                 /* Add entry for Turbo ratio */
 494                 acpigen_write_PSS_package(
 495                         clock_max + 1,          /*MHz*/
 496                         power_max,              /*mW*/
 497                         PSS_LATENCY_TRANSITION, /*lat1*/
 498                         PSS_LATENCY_BUSMASTER,  /*lat2*/
 499                         ratio_turbo << 8,       /*control*/
 500                         ratio_turbo << 8);      /*status*/
 501         } else {
 502                 /* _PSS package count without Turbo */
 503                 acpigen_write_package(num_entries + 1);
 504         }
 505
 506         /* First regular entry is max non-turbo ratio */
 507         acpigen_write_PSS_package(
 508                 clock_max,              /*MHz*/
 509                 power_max,              /*mW*/
 510                 PSS_LATENCY_TRANSITION, /*lat1*/
 511                 PSS_LATENCY_BUSMASTER,  /*lat2*/
 512                 ratio_max << 8,         /*control*/
 513                 ratio_max << 8);        /*status*/
 514
 515         /* Generate the remaining entries */
 516         for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 517              ratio >= ratio_min; ratio -= ratio_step) {
 518
 519                 /* Calculate power at this ratio */
 520                 power = calculate_power(power_max, ratio_max, ratio);
 521                 clock = ratio * CPU_BCLK;
 522
 523                 acpigen_write_PSS_package(
 524                         clock,                  /*MHz*/
 525                         power,                  /*mW*/
 526                         PSS_LATENCY_TRANSITION, /*lat1*/
 527                         PSS_LATENCY_BUSMASTER,  /*lat2*/
 528                         ratio << 8,             /*control*/
 529                         ratio << 8);            /*status*/
 530         }
 531
 532         /* Fix package length */
 533         acpigen_pop_len();
 534 }
 535
 536 void generate_cpu_entries(device_t device)
 537 {
 538         int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
 539         int totalcores = dev_count_cpu();
 540         int cores_per_package = get_cores_per_package();
 541         int numcpus = totalcores/cores_per_package;
 542
 543         printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
 544                numcpus, cores_per_package);
 545
 546         for (cpuID=1; cpuID <=numcpus; cpuID++) {
 547                 for (coreID=1; coreID<=cores_per_package; coreID++) {
 548                         if (coreID>1) {
 549                                 pcontrol_blk = 0;
 550                                 plen = 0;
 551                         }
 552
 553                         /* Generate processor \_PR.CPUx */
 554                         acpigen_write_processor(
 555                                 (cpuID-1)*cores_per_package+coreID-1,
 556                                 pcontrol_blk, plen);
 557
 558                         /* Generate P-state tables */
 559                         generate_P_state_entries(
 560                                 coreID-1, cores_per_package);
 561
 562                         /* Generate C-state tables */
 563                         generate_C_state_entries();
 564
 565                         /* Generate T-state tables */
 566                         generate_T_state_entries(
 567                                 cpuID-1, cores_per_package);
 568
 569                         acpigen_pop_len();
 570                 }
 571         }
 572 }
 573
 574 unsigned long acpi_madt_irq_overrides(unsigned long current)
 575 {
 576         int sci = acpi_sci_irq();
 577         acpi_madt_irqoverride_t *irqovr;
 578         uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
 579
 580         /* INT_SRC_OVR */
 581         irqovr = (void *)current;
 582         current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
 583
 584         if (sci >= 20)
 585                 flags |= MP_IRQ_POLARITY_LOW;
 586         else
 587                 flags |= MP_IRQ_POLARITY_HIGH;
 588
 589         /* SCI */
 590         irqovr = (void *)current;
 591         current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags);
 592
 593         return current;
 594 }