src/soc/intel/braswell/lpe.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Google Inc.
   5  * Copyright (C) 2015 Intel Corp.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include <cbmem.h>
  19 #include <console/console.h>
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ids.h>
  23 #include <reg_script.h>
  24
  25 #include <soc/iomap.h>
  26 #include <soc/iosf.h>
  27 #include <soc/lpc.h>
  28 #include <soc/nvs.h>
  29 #include <soc/pattrs.h>
  30 #include <soc/pci_devs.h>
  31 #include <soc/pm.h>
  32 #include <soc/ramstage.h>
  33 #include "chip.h"
  34
  35
  36 /*
  37  * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB
  38  * address. Just take 1MiB @ 512MiB.
  39  */
  40 #define FIRMWARE_PHYS_BASE (512 << 20)
  41 #define FIRMWARE_PHYS_LENGTH (1 << 20)
  42 #define FIRMWARE_PCI_REG_BASE 0xa8
  43 #define FIRMWARE_PCI_REG_LENGTH 0xac
  44 #define FIRMWARE_REG_BASE_C0 0x144000
  45 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
  46
  47 static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
  48 {
  49         struct resource *res;
  50
  51         res = find_resource(dev, index);
  52         if (res)
  53                 *field = res->base;
  54 }
  55
  56 static void lpe_enable_acpi_mode(device_t dev)
  57 {
  58         static const struct reg_script ops[] = {
  59                 /* Disable PCI interrupt, enable Memory and Bus Master */
  60                 REG_PCI_OR32(PCI_COMMAND,
  61                              PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
  62                              | PCI_COMMAND_INT_DISABLE),
  63                 /* Enable ACPI mode */
  64                 REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1,
  65                             LPE_PCICFGCTR1_PCI_CFG_DIS |
  66                             LPE_PCICFGCTR1_ACPI_INT_EN),
  67                 REG_SCRIPT_END
  68         };
  69         global_nvs_t *gnvs;
  70
  71         /* Find ACPI NVS to update BARs */
  72         gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
  73         if (!gnvs) {
  74                 printk(BIOS_ERR, "Unable to locate Global NVS\n");
  75                 return;
  76         }
  77
  78         /* Save BAR0, BAR1, and firmware base  to ACPI NVS */
  79         assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
  80         /* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */
  81         /* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);  */
  82         assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
  83
  84         /* Device is enabled in ACPI mode */
  85         gnvs->dev.lpe_en = 1;
  86
  87         /* Put device in ACPI mode */
  88         reg_script_run_on_dev(dev, ops);
  89 }
  90
  91 static void setup_codec_clock(device_t dev)
  92 {
  93         uint32_t reg;
  94         u32 *clk_reg;
  95         struct soc_intel_braswell_config *config;
  96         const char *freq_str;
  97
  98         config = dev->chip_info;
  99         switch (config->lpe_codec_clk_freq) {
 100         case 19:
 101                 freq_str = "19.2";
 102                 reg = CLK_FREQ_19P2MHZ;
 103                 break;
 104         case 25:
 105                 freq_str = "25";
 106                 reg = CLK_FREQ_25MHZ;
 107                 break;
 108         default:
 109                 printk(BIOS_DEBUG, "LPE codec clock not required.\n");
 110                 return;
 111         }
 112
 113         /* Default to always running. */
 114         reg |= CLK_CTL_ON;
 115
 116         if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) {
 117                 printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n");
 118                 return;
 119         }
 120
 121         printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
 122
 123         clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
 124         clk_reg += config->lpe_codec_clk_num;
 125
 126         write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
 127 }
 128
 129 static void lpe_stash_firmware_info(device_t dev)
 130 {
 131         struct resource *res;
 132         struct resource *mmio;
 133
 134         res = find_resource(dev, FIRMWARE_PCI_REG_BASE);
 135         if (res == NULL) {
 136                 printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
 137                 return;
 138         }
 139         printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base);
 140
 141         /* Continue using old way of informing firmware address / size. */
 142         pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base);
 143         pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size);
 144
 145         /* Also put the address in MMIO space like on C0 BTM */
 146         mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
 147         write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), \
 148                 res->base);
 149         write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), \
 150                 res->size);
 151 }
 152
 153
 154 static void lpe_init(device_t dev)
 155 {
 156         struct soc_intel_braswell_config *config = dev->chip_info;
 157
 158         printk(BIOS_SPEW, "%s/%s ( %s )\n",
 159                         __FILE__, __func__, dev_name(dev));
 160
 161         lpe_stash_firmware_info(dev);
 162         setup_codec_clock(dev);
 163
 164         if (config->lpe_acpi_mode)
 165                 lpe_enable_acpi_mode(dev);
 166 }
 167
 168 static void lpe_read_resources(device_t dev)
 169 {
 170         pci_dev_read_resources(dev);
 171
 172         reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE,
 173                               FIRMWARE_PHYS_BASE >> 10,
 174                               FIRMWARE_PHYS_LENGTH >> 10);
 175 }
 176
 177 static const struct device_operations device_ops = {
 178         .read_resources         = lpe_read_resources,
 179         .set_resources          = pci_dev_set_resources,
 180         .enable_resources       = pci_dev_enable_resources,
 181         .init                   = lpe_init,
 182         .enable                 = NULL,
 183         .scan_bus               = NULL,
 184         .ops_pci                = &soc_pci_ops,
 185 };
 186
 187 static const struct pci_driver southcluster __pci_driver = {
 188         .ops            = &device_ops,
 189         .vendor         = PCI_VENDOR_ID_INTEL,
 190         .device         = LPE_DEVID,
 191 };