2 * This file is part of the coreboot project.
4 * Copyright (C) 2015 Google Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #ifndef DPTF_CPU_PASSIVE
18 #define DPTF_CPU_PASSIVE 80
21 #ifndef DPTF_CPU_CRITICAL
22 #define DPTF_CPU_CRITICAL 90
25 #ifndef DPTF_CPU_ACTIVE_AC0
26 #define DPTF_CPU_ACTIVE_AC0 90
29 #ifndef DPTF_CPU_ACTIVE_AC1
30 #define DPTF_CPU_ACTIVE_AC1 80
33 #ifndef DPTF_CPU_ACTIVE_AC2
34 #define DPTF_CPU_ACTIVE_AC2 70
37 #ifndef DPTF_CPU_ACTIVE_AC3
38 #define DPTF_CPU_ACTIVE_AC3 60
41 #ifndef DPTF_CPU_ACTIVE_AC4
42 #define DPTF_CPU_ACTIVE_AC4 50
45 External (\_PR.CP00._TSS, MethodObj)
46 External (\_PR.CP00._TPC, MethodObj)
47 External (\_PR.CP00._PTC, PkgObj)
48 External (\_PR.CP00._TSD, PkgObj)
49 External (\_PR.CP00._PSS, MethodObj)
50 External (\_SB.DPTF.CTOK, MethodObj)
54 Name (_ADR, 0x000B0000) /* Bus 0, Device B, Function 0 */
58 If (LEqual (\DPTE, One)) {
66 * Processor Throttling Controls
71 If (CondRefOf (\_PR.CP00._TSS)) {
72 Return (\_PR.CP00._TSS)
76 Package () { 0, 0, 0, 0, 0 }
83 If (CondRefOf (\_PR.CP00._TPC)) {
84 Return (\_PR.CP00._TPC)
92 If (CondRefOf (\_PR.CP00._PTC)) {
93 Return (\_PR.CP00._PTC)
105 If (CondRefOf (\_PR.CP00._TSD)) {
106 Return (\_PR.CP00._TSD)
110 Package () { 5, 0, 0, 0, 0 }
117 If (CondRefOf (\_PR.CP00._TSS)) {
118 Store (SizeOf (\_PR.CP00._TSS ()), Local0)
127 * Processor Performance Control
139 /* Notify OS to re-read _PPC limit on each CPU */
145 If (CondRefOf (\_PR.CP00._PSS)) {
146 Return (\_PR.CP00._PSS)
150 Package () { 0, 0, 0, 0, 0, 0 }
157 /* Check for mainboard specific _PDL override */
158 If (CondRefOf (\_SB.MPDL)) {
160 } ElseIf (CondRefOf (\_PR.CP00._PSS)) {
161 Store (SizeOf (\_PR.CP00._PSS ()), Local0)
169 /* Return PPCC table defined by mainboard */
177 Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL))
182 Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE))
187 Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0))
192 Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1))
197 Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2))
202 Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3))
207 Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4))