src/soc/intel/braswell/acpi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  * Copyright (C) 2013 Google Inc.
   6  * Copyright (C) 2015 Intel Corp.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <arch/acpi.h>
  19 #include <arch/acpigen.h>
  20 #include <arch/cpu.h>
  21 #include <arch/io.h>
  22 #include <arch/smp/mpspec.h>
  23 #include <cbfs.h>
  24 #include <cbmem.h>
  25 #include <console/console.h>
  26 #include <cpu/cpu.h>
  27 #include <cpu/intel/turbo.h>
  28 #include <cpu/x86/msr.h>
  29 #include <cpu/x86/smm.h>
  30 #include <cpu/x86/tsc.h>
  31 #include <device/pci.h>
  32 #include <device/pci_ids.h>
  33 #include <ec/google/chromeec/ec.h>
  34 #include <fsp/gop.h>
  35 #include <rules.h>
  36 #include <soc/acpi.h>
  37 #include <soc/gfx.h>
  38 #include <soc/iomap.h>
  39 #include <soc/irq.h>
  40 #include <soc/msr.h>
  41 #include <soc/pattrs.h>
  42 #include <soc/pci_devs.h>
  43 #include <soc/pm.h>
  44 #include <string.h>
  45 #include <types.h>
  46 #include <vendorcode/google/chromeos/gnvs.h>
  47
  48 #define MWAIT_RES(state, sub_state)                         \
  49         {                                                   \
  50                 .addrl = (((state) << 4) | (sub_state)),    \
  51                 .space_id = ACPI_ADDRESS_SPACE_FIXED,       \
  52                 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,    \
  53                 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,    \
  54                 .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
  55         }
  56
  57 /* C-state map without S0ix */
  58 static acpi_cstate_t cstate_map[] = {
  59         {
  60                 /* C1 */
  61                 .ctype = 1, /* ACPI C1 */
  62                 .latency = 1,
  63                 .power = 1000,
  64                 .resource = MWAIT_RES(0, 0),
  65         },
  66         {
  67                 /* C6NS with no L2 shrink */
  68                 /* NOTE: this substate is above CPUID limit */
  69                 .ctype = 2, /* ACPI C2 */
  70                 .latency = 500,
  71                 .power = 10,
  72                 .resource = MWAIT_RES(5, 1),
  73         },
  74         {
  75                 /* C6FS with full L2 shrink */
  76                 .ctype = 3, /* ACPI C3 */
  77                 .latency = 1500, /* 1.5ms worst case */
  78                 .power = 1,
  79                 .resource = MWAIT_RES(5, 2),
  80         }
  81 };
  82
  83 void acpi_init_gnvs(global_nvs_t *gnvs)
  84 {
  85         /* Set unknown wake source */
  86         gnvs->pm1i = -1;
  87
  88         /* CPU core count */
  89         gnvs->pcnt = dev_count_cpu();
  90
  91         /* Top of Low Memory (start of resource allocation) */
  92         gnvs->tolm = nc_read_top_of_low_memory();
  93
  94 #if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
  95         /* Update the mem console pointer. */
  96         gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
  97 #endif
  98
  99 #if IS_ENABLED(CONFIG_CHROMEOS)
 100         /* Initialize Verified Boot data */
 101         chromeos_init_vboot(&(gnvs->chromeos));
 102 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 103         gnvs->chromeos.vbt2 = google_ec_running_ro() ?
 104                 ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
 105 #endif
 106 #endif
 107 }
 108
 109 static int acpi_sci_irq(void)
 110 {
 111         u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
 112         int scis;
 113         static int sci_irq;
 114
 115         if (sci_irq)
 116                 return sci_irq;
 117
 118         /* Determine how SCI is routed. */
 119         scis = read32(actl) & SCIS_MASK;
 120         switch (scis) {
 121         case SCIS_IRQ9:
 122         case SCIS_IRQ10:
 123         case SCIS_IRQ11:
 124                 sci_irq = scis - SCIS_IRQ9 + 9;
 125                 break;
 126         case SCIS_IRQ20:
 127         case SCIS_IRQ21:
 128         case SCIS_IRQ22:
 129         case SCIS_IRQ23:
 130                 sci_irq = scis - SCIS_IRQ20 + 20;
 131                 break;
 132         default:
 133                 printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
 134                 sci_irq = 9;
 135                 break;
 136         }
 137
 138         printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
 139         return sci_irq;
 140 }
 141
 142 unsigned long acpi_fill_mcfg(unsigned long current)
 143 {
 144         current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
 145                                              MCFG_BASE_ADDRESS, 0, 0, 255);
 146         return current;
 147 }
 148
 149 void acpi_fill_in_fadt(acpi_fadt_t *fadt)
 150 {
 151         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 152
 153         fadt->sci_int = acpi_sci_irq();
 154         fadt->smi_cmd = APM_CNT;
 155         fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
 156         fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 157         fadt->s4bios_req = 0x0;
 158         fadt->pstate_cnt = 0;
 159
 160         fadt->pm1a_evt_blk = pmbase + PM1_STS;
 161         fadt->pm1b_evt_blk = 0x0;
 162         fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
 163         fadt->pm1b_cnt_blk = 0x0;
 164         fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK;
 165         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 166         fadt->gpe0_blk = pmbase + GPE0_STS;
 167         fadt->gpe1_blk = 0;
 168
 169         fadt->pm1_evt_len = 4;
 170         fadt->pm1_cnt_len = 2;
 171         fadt->pm2_cnt_len = 1;
 172         fadt->pm_tmr_len = 4;
 173         fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS);
 174         fadt->gpe1_blk_len = 0;
 175         fadt->gpe1_base = 0;
 176         fadt->cst_cnt = 0;
 177         fadt->p_lvl2_lat = 1;
 178         fadt->p_lvl3_lat = 87;
 179         fadt->flush_size = 1024;
 180         fadt->flush_stride = 16;
 181         fadt->duty_offset = 1;
 182         fadt->duty_width = 0;
 183         fadt->day_alrm = 0xd;
 184         fadt->mon_alrm = 0x00;
 185         fadt->century = 0x00;
 186         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
 187
 188         fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
 189                         ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
 190                         ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
 191                         ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
 192
 193         fadt->reset_reg.space_id = 1;
 194         fadt->reset_reg.bit_width = 8;
 195         fadt->reset_reg.bit_offset = 0;
 196         fadt->reset_reg.resv = 0;
 197         fadt->reset_reg.addrl = 0xcf9;
 198         fadt->reset_reg.addrh = 0;
 199         fadt->reset_value = 6;
 200
 201         fadt->x_pm1a_evt_blk.space_id = 1;
 202         fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
 203         fadt->x_pm1a_evt_blk.bit_offset = 0;
 204         fadt->x_pm1a_evt_blk.resv = 0;
 205         fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
 206         fadt->x_pm1a_evt_blk.addrh = 0x0;
 207
 208         fadt->x_pm1b_evt_blk.space_id = 1;
 209         fadt->x_pm1b_evt_blk.bit_width = 0;
 210         fadt->x_pm1b_evt_blk.bit_offset = 0;
 211         fadt->x_pm1b_evt_blk.resv = 0;
 212         fadt->x_pm1b_evt_blk.addrl = 0x0;
 213         fadt->x_pm1b_evt_blk.addrh = 0x0;
 214
 215         fadt->x_pm1a_cnt_blk.space_id = 1;
 216         fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
 217         fadt->x_pm1a_cnt_blk.bit_offset = 0;
 218         fadt->x_pm1a_cnt_blk.resv = 0;
 219         fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
 220         fadt->x_pm1a_cnt_blk.addrh = 0x0;
 221
 222         fadt->x_pm1b_cnt_blk.space_id = 1;
 223         fadt->x_pm1b_cnt_blk.bit_width = 0;
 224         fadt->x_pm1b_cnt_blk.bit_offset = 0;
 225         fadt->x_pm1b_cnt_blk.resv = 0;
 226         fadt->x_pm1b_cnt_blk.addrl = 0x0;
 227         fadt->x_pm1b_cnt_blk.addrh = 0x0;
 228
 229         fadt->x_pm2_cnt_blk.space_id = 1;
 230         fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
 231         fadt->x_pm2_cnt_blk.bit_offset = 0;
 232         fadt->x_pm2_cnt_blk.resv = 0;
 233         fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK;
 234         fadt->x_pm2_cnt_blk.addrh = 0x0;
 235
 236         fadt->x_pm_tmr_blk.space_id = 1;
 237         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 238         fadt->x_pm_tmr_blk.bit_offset = 0;
 239         fadt->x_pm_tmr_blk.resv = 0;
 240         fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
 241         fadt->x_pm_tmr_blk.addrh = 0x0;
 242
 243         fadt->x_gpe0_blk.space_id = 1;
 244         fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
 245         fadt->x_gpe0_blk.bit_offset = 0;
 246         fadt->x_gpe0_blk.resv = 0;
 247         fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
 248         fadt->x_gpe0_blk.addrh = 0x0;
 249
 250         fadt->x_gpe1_blk.space_id = 1;
 251         fadt->x_gpe1_blk.bit_width = 0;
 252         fadt->x_gpe1_blk.bit_offset = 0;
 253         fadt->x_gpe1_blk.resv = 0;
 254         fadt->x_gpe1_blk.addrl = 0x0;
 255         fadt->x_gpe1_blk.addrh = 0x0;
 256 }
 257
 258 static acpi_tstate_t soc_tss_table[] = {
 259         { 100, 1000, 0, 0x00, 0 },
 260         { 88, 875, 0, 0x1e, 0 },
 261         { 75, 750, 0, 0x1c, 0 },
 262         { 63, 625, 0, 0x1a, 0 },
 263         { 50, 500, 0, 0x18, 0 },
 264         { 38, 375, 0, 0x16, 0 },
 265         { 25, 250, 0, 0x14, 0 },
 266         { 13, 125, 0, 0x12, 0 },
 267 };
 268
 269 static void generate_t_state_entries(int core, int cores_per_package)
 270 {
 271         /* Indicate SW_ALL coordination for T-states */
 272         acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
 273
 274         /* Indicate FFixedHW so OS will use MSR */
 275         acpigen_write_empty_PTC();
 276
 277         /* Set NVS controlled T-state limit */
 278         acpigen_write_TPC("\\TLVL");
 279
 280         /* Write TSS table for MSR access */
 281         acpigen_write_TSS_package(
 282                 ARRAY_SIZE(soc_tss_table), soc_tss_table);
 283 }
 284
 285 static int calculate_power(int tdp, int p1_ratio, int ratio)
 286 {
 287         u32 m;
 288         u32 power;
 289
 290         /*
 291          * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
 292          *
 293          * Power = (ratio / p1_ratio) * m * tdp
 294          */
 295
 296         m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
 297         m = (m * m) / 1000;
 298
 299         power = ((ratio * 100000 / p1_ratio) / 100);
 300         power *= (m / 100) * (tdp / 1000);
 301         power /= 1000;
 302
 303         return (int)power;
 304 }
 305
 306 static void generate_p_state_entries(int core, int cores_per_package)
 307 {
 308         int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2;
 309         int coord_type, power_max, power_unit, num_entries;
 310         int ratio, power, clock, clock_max;
 311         int vid, vid_turbo, vid_min, vid_max, vid_range_2;
 312         u32 control_status;
 313         const struct pattrs *pattrs = pattrs_get();
 314         msr_t msr;
 315
 316         /* Inputs from CPU attributes */
 317         ratio_max = pattrs->iacore_ratios[IACORE_MAX];
 318         ratio_min = pattrs->iacore_ratios[IACORE_LFM];
 319         vid_max = pattrs->iacore_vids[IACORE_MAX];
 320         vid_min = pattrs->iacore_vids[IACORE_LFM];
 321
 322         /* Set P-states coordination type based on MSR disable bit */
 323         coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL;
 324
 325         /* Max Non-Turbo Frequency */
 326         clock_max = (ratio_max * pattrs->bclk_khz) / 1000;
 327
 328         /* Calculate CPU TDP in mW */
 329         msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
 330         power_unit = 1 << (msr.lo & 0xf);
 331         msr = rdmsr(MSR_PKG_POWER_LIMIT);
 332         power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
 333
 334         /* Write _PCT indicating use of FFixedHW */
 335         acpigen_write_empty_PCT();
 336
 337         /* Write _PPC with NVS specified limit on supported P-state */
 338         acpigen_write_PPC_NVS();
 339
 340         /* Write PSD indicating configured coordination type */
 341         acpigen_write_PSD_package(core, 1, coord_type);
 342
 343         /* Add P-state entries in _PSS table */
 344         acpigen_write_name("_PSS");
 345
 346         /* Determine ratio points */
 347         ratio_step = 1;
 348         num_entries = (ratio_max - ratio_min) / ratio_step;
 349         while (num_entries > 15) { /* ACPI max is 15 ratios */
 350                 ratio_step <<= 1;
 351                 num_entries >>= 1;
 352         }
 353
 354         /* P[T] is Turbo state if enabled */
 355         if (get_turbo_state() == TURBO_ENABLED) {
 356                 /* _PSS package count including Turbo */
 357                 acpigen_write_package(num_entries + 2);
 358
 359                 ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO];
 360                 vid_turbo = pattrs->iacore_vids[IACORE_TURBO];
 361                 control_status = (ratio_turbo << 8) | vid_turbo;
 362
 363                 /* Add entry for Turbo ratio */
 364                 acpigen_write_PSS_package(
 365                         clock_max + 1,          /* MHz */
 366                         power_max,              /* mW */
 367                         10,                     /* lat1 */
 368                         10,                     /* lat2 */
 369                         control_status,         /* control */
 370                         control_status);        /* status */
 371         } else {
 372                 /* _PSS package count without Turbo */
 373                 acpigen_write_package(num_entries + 1);
 374                 ratio_turbo = ratio_max;
 375                 vid_turbo = vid_max;
 376         }
 377
 378         /* First regular entry is max non-turbo ratio */
 379         control_status = (ratio_max << 8) | vid_max;
 380         acpigen_write_PSS_package(
 381                 clock_max,              /* MHz */
 382                 power_max,              /* mW */
 383                 10,                     /* lat1 */
 384                 10,                     /* lat2 */
 385                 control_status,         /* control */
 386                 control_status);        /* status */
 387
 388         /* Set up ratio and vid ranges for VID calculation */
 389         ratio_range_2 = (ratio_turbo - ratio_min) * 2;
 390         vid_range_2 = (vid_turbo - vid_min) * 2;
 391
 392         /* Generate the remaining entries */
 393         for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 394              ratio >= ratio_min; ratio -= ratio_step) {
 395
 396                 /* Calculate VID for this ratio */
 397                 vid = ((ratio - ratio_min) * vid_range_2) /
 398                         ratio_range_2 + vid_min;
 399                 /* Round up if remainder */
 400                 if (((ratio - ratio_min) * vid_range_2) % ratio_range_2)
 401                         vid++;
 402
 403                 /* Calculate power at this ratio */
 404                 power = calculate_power(power_max, ratio_max, ratio);
 405                 clock = (ratio * pattrs->bclk_khz) / 1000;
 406                 control_status = (ratio << 8) | (vid & 0xff);
 407
 408                 acpigen_write_PSS_package(
 409                         clock,                  /* MHz */
 410                         power,                  /* mW */
 411                         10,                     /* lat1 */
 412                         10,                     /* lat2 */
 413                         control_status,         /* control */
 414                         control_status);        /* status */
 415         }
 416
 417         /* Fix package length */
 418         acpigen_pop_len();
 419 }
 420
 421 void generate_cpu_entries(device_t device)
 422 {
 423         int core;
 424         int pcontrol_blk = get_pmbase(), plen = 6;
 425         const struct pattrs *pattrs = pattrs_get();
 426
 427         for (core = 0; core < pattrs->num_cpus; core++) {
 428                 if (core > 0) {
 429                         pcontrol_blk = 0;
 430                         plen = 0;
 431                 }
 432
 433                 /* Generate processor \_PR.CPUx */
 434                 acpigen_write_processor(
 435                         core, pcontrol_blk, plen);
 436
 437                 /* Generate  P-state tables */
 438                 generate_p_state_entries(
 439                         core, pattrs->num_cpus);
 440
 441                 /* Generate C-state tables */
 442                 acpigen_write_CST_package(
 443                         cstate_map, ARRAY_SIZE(cstate_map));
 444
 445                 /* Generate T-state tables */
 446                 generate_t_state_entries(
 447                         core, pattrs->num_cpus);
 448
 449                 acpigen_pop_len();
 450         }
 451 }
 452
 453 unsigned long acpi_madt_irq_overrides(unsigned long current)
 454 {
 455         int sci_irq = acpi_sci_irq();
 456         acpi_madt_irqoverride_t *irqovr;
 457         uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL;
 458
 459         /* INT_SRC_OVR */
 460         irqovr = (void *)current;
 461         current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
 462
 463         if (sci_irq >= 20)
 464                 sci_flags |= MP_IRQ_POLARITY_LOW;
 465         else
 466                 sci_flags |= MP_IRQ_POLARITY_HIGH;
 467
 468         irqovr = (void *)current;
 469         current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
 470                                                 sci_flags);
 471
 472         return current;
 473 }
 474
 475 #define ALIGN_CURRENT current = (ALIGN(current, 16))
 476
 477 unsigned long southcluster_write_acpi_tables(device_t device,
 478                                              unsigned long current,
 479                                              struct acpi_rsdp *rsdp)
 480 {
 481         acpi_header_t *ssdt2;
 482
 483         current = acpi_write_hpet(device, current, rsdp);
 484         ALIGN_CURRENT;
 485
 486 #if CONFIG_GOP_SUPPORT
 487         igd_opregion_t *opregion;
 488
 489         printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
 490         opregion = (igd_opregion_t *)current;
 491         init_igd_opregion(opregion);
 492         current += sizeof(igd_opregion_t);
 493         ALIGN_CURRENT;
 494 #endif
 495
 496         ssdt2 = (acpi_header_t *)current;
 497         memset(ssdt2, 0, sizeof(acpi_header_t));
 498         acpi_create_serialio_ssdt(ssdt2);
 499         if (ssdt2->length) {
 500                 current += ssdt2->length;
 501                 acpi_add_table(rsdp, ssdt2);
 502                 printk(BIOS_DEBUG, "ACPI:     * SSDT2 @ %p Length %x\n",ssdt2,
 503                        ssdt2->length);
 504                 ALIGN_CURRENT;
 505         } else {
 506                 ssdt2 = NULL;
 507                 printk(BIOS_DEBUG, "ACPI:     * SSDT2 not generated.\n");
 508         }
 509
 510         printk(BIOS_DEBUG, "current = %lx\n", current);
 511
 512         return current;
 513 }
 514
 515 void southcluster_inject_dsdt(device_t device)
 516 {
 517         global_nvs_t *gnvs;
 518
 519         gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 520         if (!gnvs) {
 521                 gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
 522                 if (gnvs)
 523                         memset(gnvs, 0, sizeof(*gnvs));
 524         }
 525
 526         if (gnvs) {
 527                 acpi_create_gnvs(gnvs);
 528                 acpi_save_gnvs((unsigned long)gnvs);
 529                 /* And tell SMI about it */
 530                 smm_setup_structures(gnvs, NULL, NULL);
 531
 532                 /* Add it to DSDT.  */
 533                 acpigen_write_scope("\\");
 534                 acpigen_write_name_dword("NVSA", (u32) gnvs);
 535                 acpigen_pop_len();
 536         }
 537 }
 538
 539 __attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
 540 {
 541 }
 542
 543 #if CONFIG_GOP_SUPPORT
 544 /* Reading VBT table from flash */
 545 static void get_fsp_vbt(igd_opregion_t *opregion)
 546 {
 547         const optionrom_vbt_t *vbt;
 548         uint32_t vbt_len;
 549
 550         vbt = fsp_get_vbt(&vbt_len);
 551         if (!vbt)
 552                 die("vbt data not found");
 553         memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
 554         memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
 555                 sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
 556                 sizeof(opregion->vbt.gvd1));
 557 }
 558
 559 /* Initialize IGD OpRegion, called from ACPI code */
 560 int init_igd_opregion(igd_opregion_t *opregion)
 561 {
 562         device_t igd;
 563         u16 reg16;
 564
 565         memset(opregion, 0, sizeof(igd_opregion_t));
 566
 567         /* FIXME if IGD is disabled, we should exit here. */
 568
 569         memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
 570                 sizeof(IGD_OPREGION_SIGNATURE));
 571
 572         /* 8kb */
 573         opregion->header.size = sizeof(igd_opregion_t) / 1024;
 574         opregion->header.version = IGD_OPREGION_VERSION;
 575
 576         /* FIXME We just assume we're mobile for now */
 577         opregion->header.mailboxes = MAILBOXES_MOBILE;
 578
 579         /* TODO Initialize Mailbox 1 */
 580
 581         /* TODO Initialize Mailbox 3 */
 582         opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
 583         opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
 584         opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
 585         opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
 586         opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
 587         opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
 588         opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
 589         opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
 590         opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
 591         opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
 592         opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
 593         opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
 594         opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
 595         opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
 596         opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
 597
 598         get_fsp_vbt(opregion);
 599
 600         /*
 601          * TODO This needs to happen in S3 resume, too.
 602          * Maybe it should move to the finalize handler
 603          */
 604         igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC));
 605
 606         pci_write_config32(igd, ASLS, (u32)opregion);
 607         reg16 = pci_read_config16(igd, SWSCI);
 608         reg16 &= ~(1 << 0);
 609         reg16 |= (1 << 15);
 610         pci_write_config16(igd, SWSCI, reg16);
 611
 612         return 0;
 613 }
 614 #endif