src/soc/intel/baytrail/romstage/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stddef.h>
  17 #include <arch/cpu.h>
  18 #include <arch/io.h>
  19 #include <arch/stages.h>
  20 #include <arch/early_variables.h>
  21 #include <console/console.h>
  22 #include <cbfs.h>
  23 #include <cbmem.h>
  24 #include <cpu/x86/mtrr.h>
  25 #if CONFIG_EC_GOOGLE_CHROMEEC
  26 #include <ec/google/chromeec/ec.h>
  27 #endif
  28 #include <elog.h>
  29 #include <romstage_handoff.h>
  30 #include <stage_cache.h>
  31 #include <timestamp.h>
  32 #include <tpm.h>
  33 #include <vendorcode/google/chromeos/chromeos.h>
  34 #include <soc/gpio.h>
  35 #include <soc/iomap.h>
  36 #include <soc/lpc.h>
  37 #include <soc/pci_devs.h>
  38 #include <soc/pmc.h>
  39 #include <soc/reset.h>
  40 #include <soc/romstage.h>
  41 #include <soc/smm.h>
  42 #include <soc/spi.h>
  43
  44 /* The cache-as-ram assembly file calls romstage_main() after setting up
  45  * cache-as-ram.  romstage_main() will then call the mainboards's
  46  * mainboard_romstage_entry() function. That function then calls
  47  * romstage_common() below. The reason for the back and forth is to provide
  48  * common entry point from cache-as-ram while still allowing for code sharing.
  49  * Because we can't use global variables the stack is used for allocations --
  50  * thus the need to call back and forth. */
  51
  52 static void *setup_stack_and_mttrs(void);
  53
  54 static void program_base_addresses(void)
  55 {
  56         uint32_t reg;
  57         const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
  58
  59         /* Memory Mapped IO registers. */
  60         reg = PMC_BASE_ADDRESS | 2;
  61         pci_write_config32(lpc_dev, PBASE, reg);
  62         reg = IO_BASE_ADDRESS | 2;
  63         pci_write_config32(lpc_dev, IOBASE, reg);
  64         reg = ILB_BASE_ADDRESS | 2;
  65         pci_write_config32(lpc_dev, IBASE, reg);
  66         reg = SPI_BASE_ADDRESS | 2;
  67         pci_write_config32(lpc_dev, SBASE, reg);
  68         reg = MPHY_BASE_ADDRESS | 2;
  69         pci_write_config32(lpc_dev, MPBASE, reg);
  70         reg = PUNIT_BASE_ADDRESS | 2;
  71         pci_write_config32(lpc_dev, PUBASE, reg);
  72         reg = RCBA_BASE_ADDRESS | 1;
  73         pci_write_config32(lpc_dev, RCBA, reg);
  74
  75         /* IO Port Registers. */
  76         reg = ACPI_BASE_ADDRESS | 2;
  77         pci_write_config32(lpc_dev, ABASE, reg);
  78         reg = GPIO_BASE_ADDRESS | 2;
  79         pci_write_config32(lpc_dev, GBASE, reg);
  80 }
  81
  82 static void spi_init(void)
  83 {
  84         u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS);
  85         u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
  86         uint32_t reg;
  87
  88         /* Disable generating SMI when setting WPD bit. */
  89         write32(scs, read32(scs) & ~SMIWPEN);
  90         /*
  91          * Enable caching and prefetching in the SPI controller. Disable
  92          * the SMM-only BIOS write and set WPD bit.
  93          */
  94         reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
  95         reg &= ~EISS;
  96         write32(bcr, reg);
  97 }
  98
  99 /* Entry from cache-as-ram.inc. */
 100 void * asmlinkage romstage_main(unsigned long bist,
 101                                 uint32_t tsc_low, uint32_t tsc_hi)
 102 {
 103         struct romstage_params rp = {
 104                 .bist = bist,
 105                 .mrc_params = NULL,
 106         };
 107
 108         /* Save initial timestamp from bootblock. */
 109         timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
 110
 111         /* Save romstage begin */
 112         timestamp_add_now(TS_START_ROMSTAGE);
 113
 114         program_base_addresses();
 115
 116         tco_disable();
 117
 118         byt_config_com1_and_enable();
 119
 120         console_init();
 121
 122         spi_init();
 123
 124         set_max_freq();
 125
 126         punit_init();
 127
 128         gfx_init();
 129
 130 #if CONFIG_EC_GOOGLE_CHROMEEC
 131         /* Ensure the EC is in the right mode for recovery */
 132         google_chromeec_early_init();
 133 #endif
 134
 135         /* Call into mainboard. */
 136         mainboard_romstage_entry(&rp);
 137
 138         return setup_stack_and_mttrs();
 139 }
 140
 141 static struct chipset_power_state power_state CAR_GLOBAL;
 142
 143 static void migrate_power_state(int is_recovery)
 144 {
 145         struct chipset_power_state *ps_cbmem;
 146         struct chipset_power_state *ps_car;
 147
 148         ps_car = car_get_var_ptr(&power_state);
 149         ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem));
 150
 151         if (ps_cbmem == NULL) {
 152                 printk(BIOS_DEBUG, "Not adding power state to cbmem!\n");
 153                 return;
 154         }
 155         memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
 156 }
 157 ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
 158
 159 static struct chipset_power_state *fill_power_state(void)
 160 {
 161         struct chipset_power_state *ps = car_get_var_ptr(&power_state);
 162
 163         ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
 164         ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
 165         ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
 166         ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS);
 167         ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN);
 168         ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
 169         ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
 170         ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
 171         ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2));
 172
 173         printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
 174                 ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
 175         printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n",
 176                 ps->gpe0_sts, ps->gpe0_en, ps->tco_sts);
 177         printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n",
 178                 ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2);
 179
 180         return ps;
 181 }
 182
 183 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 184 static int chipset_prev_sleep_state(struct chipset_power_state *ps)
 185 {
 186         /* Default to S0. */
 187         int prev_sleep_state = 0;
 188
 189         if (ps->pm1_sts & WAK_STS) {
 190                 switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
 191         #if CONFIG_HAVE_ACPI_RESUME
 192                 case SLP_TYP_S3:
 193                         prev_sleep_state = 3;
 194                         break;
 195         #endif
 196                 case SLP_TYP_S5:
 197                         prev_sleep_state = 5;
 198                         break;
 199                 }
 200                 /* Clear SLP_TYP. */
 201                 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
 202         }
 203
 204         if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) {
 205                 prev_sleep_state = 5;
 206         }
 207
 208         return prev_sleep_state;
 209 }
 210
 211 /* Entry from the mainboard. */
 212 void romstage_common(struct romstage_params *params)
 213 {
 214         struct romstage_handoff *handoff;
 215         struct chipset_power_state *ps;
 216         int prev_sleep_state;
 217
 218         timestamp_add_now(TS_BEFORE_INITRAM);
 219
 220         ps = fill_power_state();
 221         prev_sleep_state = chipset_prev_sleep_state(ps);
 222
 223         printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
 224
 225 #if CONFIG_ELOG_BOOT_COUNT
 226         if (prev_sleep_state != 3)
 227                 boot_count_increment();
 228 #endif
 229
 230
 231         /* Initialize RAM */
 232         raminit(params->mrc_params, prev_sleep_state);
 233
 234         timestamp_add_now(TS_AFTER_INITRAM);
 235
 236         handoff = romstage_handoff_find_or_add();
 237         if (handoff != NULL)
 238                 handoff->s3_resume = (prev_sleep_state == 3);
 239         else
 240                 printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 241
 242         if (CONFIG_LPC_TPM) {
 243                 init_tpm(prev_sleep_state == 3);
 244         }
 245 }
 246
 247 void asmlinkage romstage_after_car(void)
 248 {
 249         /* Load the ramstage. */
 250         copy_and_run();
 251         while (1);
 252 }
 253
 254 static inline uint32_t *stack_push(u32 *stack, u32 value)
 255 {
 256         stack = &stack[-1];
 257         *stack = value;
 258         return stack;
 259 }
 260
 261 /* Romstage needs quite a bit of stack for decompressing images since the lzma
 262  * lib keeps its state on the stack during romstage. */
 263 static unsigned long choose_top_of_stack(void)
 264 {
 265         unsigned long stack_top;
 266         const unsigned long romstage_ram_stack_size = 0x5000;
 267
 268         /* cbmem_add() does a find() before add(). */
 269         stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
 270                                              romstage_ram_stack_size);
 271         stack_top += romstage_ram_stack_size;
 272         return stack_top;
 273 }
 274
 275 /* setup_stack_and_mttrs() determines the stack to use after
 276  * cache-as-ram is torn down as well as the MTRR settings to use. */
 277 static void *setup_stack_and_mttrs(void)
 278 {
 279         unsigned long top_of_stack;
 280         int num_mtrrs;
 281         uint32_t *slot;
 282         uint32_t mtrr_mask_upper;
 283         uint32_t top_of_ram;
 284
 285         /* Top of stack needs to be aligned to a 4-byte boundary. */
 286         top_of_stack = choose_top_of_stack() & ~3;
 287         slot = (void *)top_of_stack;
 288         num_mtrrs = 0;
 289
 290         /* The upper bits of the MTRR mask need to set according to the number
 291          * of physical address bits. */
 292         mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
 293
 294         /* The order for each MTRR is value then base with upper 32-bits of
 295          * each value coming before the lower 32-bits. The reasoning for
 296          * this ordering is to create a stack layout like the following:
 297          *   +0: Number of MTRRs
 298          *   +4: MTRR base 0 31:0
 299          *   +8: MTRR base 0 63:32
 300          *  +12: MTRR mask 0 31:0
 301          *  +16: MTRR mask 0 63:32
 302          *  +20: MTRR base 1 31:0
 303          *  +24: MTRR base 1 63:32
 304          *  +28: MTRR mask 1 31:0
 305          *  +32: MTRR mask 1 63:32
 306          */
 307
 308         /* Cache the ROM as WP just below 4GiB. */
 309         slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
 310         slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
 311         slot = stack_push(slot, 0); /* upper base */
 312         slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
 313         num_mtrrs++;
 314
 315         /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
 316         slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
 317         slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
 318         slot = stack_push(slot, 0); /* upper base */
 319         slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
 320         num_mtrrs++;
 321
 322         top_of_ram = (uint32_t)cbmem_top();
 323         /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the
 324          * start of the TSEG region. It is required to be 8MiB aligned. Set
 325          * this area as cacheable so it can be used later for ramstage before
 326          * setting up the entire RAM as cacheable. */
 327         slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
 328         slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
 329         slot = stack_push(slot, 0); /* upper base */
 330         slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
 331         num_mtrrs++;
 332
 333         /* Cache 8MiB at the top of ram. Top of ram is where the TSEG
 334          * region resides. However, it is not restricted to SMM mode until
 335          * SMM has been relocated. By setting the region to cacheable it
 336          * provides faster access when relocating the SMM handler as well
 337          * as using the TSEG region for other purposes. */
 338         slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
 339         slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
 340         slot = stack_push(slot, 0); /* upper base */
 341         slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
 342         num_mtrrs++;
 343
 344         /* Save the number of MTRRs to setup. Return the stack location
 345          * pointing to the number of MTRRs. */
 346         slot = stack_push(slot, num_mtrrs);
 347
 348         return slot;
 349 }
 350
 351 void ramstage_cache_invalid(void)
 352 {
 353 #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
 354         /* Perform cold reset on invalid ramstage cache. */
 355         cold_reset();
 356 #endif
 357 }
 358
 359 int get_sw_write_protect_state(void)
 360 {
 361         u8 status;
 362         /* Return unprotected status if status read fails. */
 363         return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
 364 }