src/soc/imgtec/pistachio/ddr2_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2014 Imagination Technologies
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include <soc/ddr_init.h>
  19 #include <soc/ddr_private_reg.h>
  20 #include <stdint.h>
  21
  22 #define BL8 0
  23
  24 /*
  25  * Configuration for the Winbond W972GG6JB-25 part using
  26  * Synopsys DDR uMCTL and DDR Phy
  27  */
  28 int init_ddr2(void)
  29 {
  30
  31         /*
  32          * Reset the AXI bridge and DDR Controller in case any spurious
  33          * writes have already happened to DDR - note must be done together,
  34          * not sequentially
  35          */
  36         write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000000);
  37         write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F);
  38         /*
  39          * Dummy read to fence the access between the reset above
  40          * and thw DDR controller writes below
  41          */
  42         read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
  43         /* Timings for 400MHz
  44          * therefore 200MHz (5ns) uMCTL (Internal) Rate
  45          */
  46         /* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */
  47         write32(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8);
  48         /* TINIT: t_init Timing Register: at least 200us 200h C8h */
  49         write32(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8);
  50         /* TRSTH: Reset High Time Register DDR3 ONLY */
  51         write32(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x00000000);
  52         /* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/
  53         write32(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014);
  54         /* DTUAWDT DTU Address Width Register
  55          * 1:0   column_addr_width Def 10 - 7  3 10 bits
  56          * 4:3   bank_addr_width   Def  3 - 2  1  3 bits (8 bank)
  57          * 7:6   row_addr_width    Def 14 - 13 1  3 bits
  58          * 10:9  number_ranks      Def  1 -  1 0  0 1 Rank
  59          */
  60         write32(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B);
  61         /* MCFG
  62          * 0 BL 0 = 4 1 = 8
  63          * 1 RDRIMM 0
  64          * 2 BL8 Burst Terminate 0
  65          * 3 2T = 0
  66          * 4 Multi Rank 0
  67          * 5 DDR3 En 0
  68          * 6 LPDDR S4 En
  69          * 7 BST En 0, 1 for LPDDR2/3
  70          * 15:8 Power down Idle, passed by argument
  71          * 16 Power Down Type, passed by argument
  72          * 17 Power Down Exit 0 = slow, 1 = fast, pba
  73          * 19:18 tFAW 45ns = 9 clk 5*2 -1 1h
  74          * 21:20 mDDR/LPDDR2 BL 0
  75          * 23:22 mDDR/LPDDR2 Enable 0
  76          * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0
  77          */
  78         write32(DDR_PCTL + DDR_PCTL_MCFG_OFFSET,
  79                 0x00060000 | (BL8 ? 0x1 : 0x0));
  80         /* MCFG1: Memory Configuration-1 Register
  81          * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB
  82          * 10:8 Fine tune MCFG.19:18 -1
  83          * 15:11 Reserved
  84          * 23:16 Hardware Idle Period NA 0
  85          * 30:24 Reserved
  86          * 31 c_active_in_pin exit auto clk stop NA 0
  87          */
  88         write32(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100);
  89         /* DCR DRAM Config
  90          * 2:0 SDRAM => DDR2 2
  91          * 3 DDR 8 Bank 1
  92          * 6:4 Primary DQ DDR3 Only 0
  93          * 7 Multi-Purpose Register DDR3 Only 0
  94          * 9:8 DDRTYPE LPDDR2 00
  95          * 26:10 Reserved
  96          * 27 NOSRA No Simultaneous Rank Access 0
  97          * 28 DDR 2T 0
  98          * 29 UDIMM NA 0
  99          * 30 RDIMM NA 0
 100          * 31 TPD LPDDR2 0
 101          */
 102         write32(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000A);
 103         /* Generate to use with PHY and PCTL
 104          * MR0 : MR Register, bits 12:0 imported dfrom MR
 105          * 2:0 BL 8 011
 106          * 3 BT Sequential 0 Interleaved 1 = 0
 107          * 6:4 CL 6
 108          * 7 TM Normal 0
 109          * 8 DLL Reset 1 (self Clearing)
 110          * 11:9 WR 15 ns 6 (101)
 111          * 12 PD Slow 1 Fast 0 0
 112          * 15:13 RSVD RSVD
 113          * 31:16 Reserved
 114          */
 115         write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000A62 | (BL8 ? 0x1 : 0x0));
 116         /* MR1 : EMR Register
 117          * Generate to use with PHY and PCTL
 118          * 0 DE DLL Enable 0 Disable 1
 119          * 1 DIC Output Driver Imp Ctl 0 Full, 1 Half
 120          * 6,2 ODT 0 Disable, 1 75R, 2 150R, 3 50R; LSB: 2, MSB: 6
 121          * 5:3 AL = 0
 122          * 9:7 OCD = 0
 123          * 10 DQS 0 diff, 1 single = 0
 124          * 11 RDQS NA 0
 125          * 12 QOFF Normal mode 0
 126          * 15:13 RSVD
 127          * 31:16 Reserved
 128          */
 129         write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044);
 130         /* MR2 : EMR2 Register
 131          * Generate to use with PHY and PCTL
 132          * 2:0 PASR, NA 000
 133          * 3 DDC NA 0
 134          * 6:4 RSVD
 135          * 7 SFR 0
 136          * 15:8 RSVD
 137          * 31:16 Reserved
 138          */
 139         write32(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000000);
 140         /* DSGCR
 141          * 0 PUREN Def 1
 142          * 1 BDISEN Def 1
 143          * 2 ZUEN Def 1
 144          * 3 LPIOPD DEf 1 0
 145          * 4 LPDLLPD DEf 1 0
 146          * 7:5 DQSGX DQS Extention 000
 147          * 10:8 DQSGE DQS Early Gate
 148          * 11 NOBUB No Bubbles, adds latency 1
 149          * 12 FXDLAT Fixed Read Latency 0
 150          * 15:13 Reserved
 151          * 19:16 CKEPDD CKE Power Down 0000
 152          * 23:20 ODTPDD ODT Power Down 0000
 153          * 24 NL2PD Power Down Non LPDDR2 pins 0
 154          * 25 NL2OE Output Enable Non LPDDR2 pins 1
 155          * 26 TPDPD LPDDR Only 0
 156          * 27 TPDOE LPDDR Only 0
 157          * 28 CKOE Output Enable Clk's 1
 158          * 29 ODTOE Output Enable ODT 1
 159          * 30 RSTOE RST# Output Enable 1
 160          * 31 CKEOE CKE Output Enable 1
 161          */
 162         write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000807);
 163         /* DTPR0 : DRAM Timing Params 0
 164          * 1:0 tMRD 2
 165          * 4:2 tRTP 3
 166          * 7:5 tWTR 3
 167          * 11:8 tRP 6
 168          * 15:12 tRCD 6
 169          * 20:16 tRAS 18
 170          * 24:21 tRRD 4
 171          * 30:25 tRC 24 (23)
 172          * 31 tCCD 0 BL/2 Cas to Cas
 173          */
 174         write32(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x3092666E);
 175         /* DTPR1 : DRAM Timing Params 1
 176          * 1:0 ODT On/Off Del Std 0
 177          * 2 tRTW Rd2Wr Del 0 std 1 +1 0
 178          * 8:3 tFAW 4 Bank Act 45ns = 18 18
 179          * 10:9 tMOD DDR3 Only 0
 180          * 11 tRTODT DDR3 Only 0
 181          * 15:12 Reserved
 182          * 23:16 tRFC 195ns 78 def 131 78d
 183          * 26:24 tDQSCK LPDDR2 only 1
 184          * 29:27 tDQSCKmax 1
 185          * 31:30 Reserved
 186          */
 187         write32(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094E0092);
 188         /* DTPR2 : DRAM Timing Params 2
 189          * 9:0 tXS exit SR def 200, 200d
 190          * 14:10 tXP PD Exit Del 8 3
 191          * 18:15 tCKE CKE Min pulse 3
 192          * 28:19 tDLLK DLL Lock time 200d
 193          * 32:29 Reserved
 194          */
 195         write32(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x06418CC8);
 196         /* PTR0 : PHY Timing Params 0
 197          * 5:0 tDLLRST Def 27
 198          * 17:6 tDLLLOCK Def 2750
 199          * 21:18 tITMSRST Def 8
 200          * 31:22 Reserved 0
 201          */
 202         write32(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B);
 203         /* PTR1 : PHY Timing Params 1
 204          * 18:0 : tDINITO DRAM Init time 200us 80,000 Dec 0x13880
 205          * 29:19 : tDINIT1 DRAM Init time 400ns 160 Dec 0xA0
 206          */
 207         write32(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x05013880);
 208         /* DQS gating configuration: passive windowing mode */
 209         /*
 210          * PGCR: PHY General cofiguration register
 211          * 0 ITM DDR mode: 0
 212          * 1 DQS gading configuration: passive windowing 1
 213          * 2 DQS drift compensation: not supported in passive windowing 0
 214          * 4:3 DQS drift limit 0
 215          * 8:5 Digital test output select 0
 216          * 11:9 CK Enable: one bit for each 3 CK pair: 0x7
 217          * 13:12 CK Disable values: 0x2
 218          * 14 CK Invert 0
 219          * 15 IO loopback 0
 220          * 17:16 I/O DDR mode 0
 221          * 21:18 Ranks enable by training: 0xF
 222          * 23:22 Impedance clock divider select 0x2
 223          * 24 Power down disable 1
 224          * 28:25 Refresh during training 0
 225          * 29 loopback DQS shift 0
 226          * 30 loopback DQS gating 0
 227          * 31 loopback mode 0
 228          */
 229         write32(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02);
 230         /* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */
 231         if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007))
 232                 return DDR_TIMEOUT;
 233         /* PIR : use PHY for DRAM Init */
 234         write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x000001DF);
 235         /* PGSR : Wait for DRAM Init Done */
 236         if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000001F))
 237                         return DDR_TIMEOUT;
 238         /* DF1STAT0 : wait for DFI_INIT_COMPLETE */
 239         if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET,
 240                                                 0x00000001))
 241                 return DDR_TIMEOUT;
 242         /* POWCTL : Start the memory Power Up seq*/
 243         write32(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x00000001);
 244         /* POWSTAT : wait for POWER_UP_DONE */
 245         if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET,
 246                                                 0x00000001))
 247                 return DDR_TIMEOUT;
 248         /*
 249          * TREFI : t_refi Timing Register 1X
 250          * 12:0 t_refi 7.8us in 100ns 0x4E
 251          * 15:13 Reserved 0
 252          * 18:16 num_add_ref 0
 253          * 30:19 Reserved 0
 254          * 31 Update 1
 255          */
 256         write32(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E);
 257         /* TMRD : t_mrd Timing Register -- Range 2 to 3 */
 258         write32(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000002);
 259         /*
 260          * TRFC : t_rfc Timing Register -- Range 15 to 131
 261          * 195ns / 2.5ns 78 x4E
 262          */
 263         write32(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E);
 264         /* TRP : t_rp Timing Register -- Range 3 to 7
 265          * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6
 266          * 17:16 rpea_extra tRPall 8 bank 1
 267          */
 268         write32(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00010006);
 269         /* TAL : Additive Latency Register -- AL in MR1 */
 270         write32(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000);
 271         /* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */
 272         write32(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002);
 273         /* DFITRDDATAEN : Read cmd to dfi_rddata_en */
 274         write32(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002);
 275         /* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */
 276         write32(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006);
 277         /* TCWL : CAS Write Latency Register --CASL-1 */
 278         write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005);
 279         /*
 280          * TRAS : Activate to Precharge cmd time
 281          * Range 8 to 24: 45ns / 2.5ns = 18d
 282          */
 283         write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012);
 284         /*
 285          * TRC : Min. ROW cylce time
 286          * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24
 287          */
 288         write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018);
 289         /*
 290          * TRCD : Row to Column Delay
 291          * Range 3 to 7 (TCL = TRCD): 2.5ns / 2.5ns = 5 but running 6-6-6 6
 292          */
 293         write32(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006);
 294         /* TRRD : Row to Row delay -- Range 2 to 6: 2K Page 10ns / 2.5ns = 4*/
 295         write32(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004);
 296         /* TRTP : Read to Precharge time -- Range 2 to 4: 7.3ns / 2.5ns = 3 */
 297         write32(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000003);
 298         /* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6
 299          */
 300         write32(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006);
 301         /*
 302          * TWTR : Write to read turn around time
 303          * Range 2 to 4: 7.3ns / 2.5ns = 3
 304          */
 305         write32(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000003);
 306         /* TEXSR : Exit Self Refresh to first valid cmd: tXS 200*/
 307         write32(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x000000C8);
 308         /*
 309          * TXP : Exit Power Down to first valid cmd
 310          * tXP 2, Settingto 3 to match PHY
 311          */
 312         write32(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003);
 313         /*
 314          * TDQS : t_dqs Timing Register
 315          * DQS additional turn around Rank 2 Rank (1 Rank) Def 1
 316          */
 317         write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001);
 318         /*TRTW : Read to Write turn around time Def 2
 319          * Actual gap t_bl + t_rtw
 320          */
 321         write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000002);
 322         /* TCKE : CKE min pulse width DEf 3 */
 323         write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003);
 324         /*
 325          * TXPDLL : Slow Exit Power Down to first valid cmd delay
 326          * tXARDS 10+AL = 10
 327          */
 328         write32(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A);
 329         /*
 330          * TCKESR : Min CKE Low width for Self refresh entry to exit
 331          * t_ckesr = 0 DDR2
 332          */
 333         write32(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000000);
 334         /* SCFG : State Configuration Register (Enabling Self Refresh)
 335          * 0 LP_en Leave Off for Bring Up 0
 336          * 5:1 Reserved
 337          * 6 Synopsys Internal Only 0
 338          * 7 Enale PHY indication of LP Opportunity 1
 339          * 11:8 bbflags_timing max UPCTL_TCU_SED_P - tRP (16 - 6) Use 4
 340          * 16:12 Additional delay on accertion of ac_pdd 4
 341          * 31:17 Reserved
 342          */
 343         write32(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480);
 344         /*
 345          * DFITPHYWRDATA : dfi_wrdata_en to drive wr data
 346          * DFI Clks wrdata_en to wrdata Def 1
 347          */
 348         write32(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000);
 349         /*
 350          * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid
 351          * DFI clks max rddata_en to rddata_valid Def 15
 352          */
 353         write32(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008);
 354         /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0
 355          * 3:0 cmd_opcode PREA 00001
 356          * 16:4 cmd_addr 0
 357          * 19:17 bank_addr 0
 358          * 23:20 rank_sel 0 0001
 359          * 27:24 cmddelay 0
 360          * 30:24 Reserved
 361          */
 362         write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100001);
 363         /* MRS cmd wait for completion */
 364         if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100001))
 365                 return DDR_TIMEOUT;
 366         /* SCTL : UPCTL switch INIT CONFIG State */
 367         write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001);
 368         /* STAT : Wait for Switch INIT to Config State */
 369         if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001))
 370                 return DDR_TIMEOUT;
 371         /* DFISTCFG0 : Drive various DFI signals appropriately
 372          * 0 dfi_init_start            0
 373          * 1 dfi_freq_ratio_en         1
 374          * 2 dfi_data_byte_disable_en  1
 375          */
 376         write32(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000003);
 377         /* DFISTCFG1 : Enable various DFI support
 378          * 0 dfi_dram_clk_disable_en 1
 379          * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0
 380          */
 381         write32(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001);
 382         /* DFISTCFG2 : Enable Parity and asoc interrupt
 383          * 0 dfi_parity_in Enable 1
 384          * 1 Interrupt on dfi_parity_error 1
 385          */
 386         write32(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003);
 387         /* DFILPCFG0 : DFI Low Power Interface Configuration
 388          * 0     Enable DFI LP IF during PD 1
 389          * 3:1   Reserved
 390          * 7:4   DFI tlp_wakeup time        0
 391          * 8     Enable DFI LP IF during SR 1
 392          * 11:9  Reserved
 393          * 15:12 dfi_lp_wakeup in SR        0
 394          * 19:16 tlp_resp DFI 2.1 recomend  7
 395          * 23:20 Reserved
 396          * 24    Enable DFI LP in Deep Power Down 0
 397          * 27:25 Reserved
 398          * 31:28 DFI LP Deep Power Down Value 0
 399          */
 400         write32(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101);
 401         /* DFIODTCFG : DFI ODT Configuration
 402          * Only Enabled on Rank0 Writes
 403          * 0 rank0_odt_read_nsel  0
 404          * 1 rank0_odt_read_sel   0
 405          * 2 rank0_odt_write_nsel 0
 406          * 3 rank0_odt_write_sel  1
 407          */
 408         write32(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008);
 409         /* DFIODTCFG1 : DFI ODT Configuration
 410          * 4:0   odt_lat_w     4
 411          * 12:8  odt_lat_r     0 Def
 412          * 4:0   odt_len_bl8_w 6 Def
 413          * 12:8  odt_len_bl8_r 6 Def
 414          */
 415         write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x06060004);
 416         /* DCFG : DRAM Density 256 Mb 16 Bit IO Width
 417          * 1:0  Devicw Width 1 x8, 2 x16, 3 x32  2
 418          * 5:2  Density 2Gb = 5
 419          * 6    Dram Type (MDDR/LPDDR2) Only  0
 420          * 7    Reserved 0
 421          * 10:8 Address Map R/B/C = 1
 422          * 31:11 Reserved
 423          */
 424         write32(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116);
 425         /* PCFG_0 : Port 0 AXI config  */
 426         if (BL8)
 427                 write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0);
 428         else
 429                 write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000400A0);
 430         /* SCTL : UPCTL switch Config to ACCESS State */
 431         write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002);
 432         /* STAT : Wait for switch CFG -> GO State */
 433         if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3))
 434                 return DDR_TIMEOUT;
 435
 436         return 0;
 437 }