src/northbridge/via/vx900/raminit.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me@gmail.com>
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef RAMINIT_VX900_H
  18 #define RAMINIT_VX900_H
  19
  20 #include <device/dram/ddr3.h>
  21 #include "vx900.h"
  22
  23 #define SPD_END_LIST 0xff
  24
  25 typedef struct dimm_layout_st
  26 {
  27         /* The address of the DIMM on the SMBUS *
  28          * 0xFF to terminate the array*/
  29         u8 spd_addr[VX900_MAX_DIMM_SLOTS + 1];
  30 } dimm_layout;
  31
  32 typedef struct dimm_info_st
  33 {
  34         dimm_attr dimm[VX900_MAX_DIMM_SLOTS];
  35 } dimm_info;
  36
  37 typedef struct mem_rank_st {
  38         u16 start_addr;
  39         u16 end_addr;
  40 } mem_rank;
  41
  42 typedef struct rank_layout_st {
  43         u32 phys_rank_size_mb[VX900_MAX_MEM_RANKS];
  44         mem_rank virt[VX900_MAX_MEM_RANKS];
  45         dimm_flags_t flags[VX900_MAX_MEM_RANKS];
  46 } rank_layout;
  47
  48 typedef struct pci_reg8_st {
  49         u8 addr;
  50         u8 val;
  51 } pci_reg8;
  52
  53 typedef u8 timing_dly[8];
  54
  55 typedef struct delay_range_st {
  56         timing_dly low;
  57         timing_dly avg;
  58         timing_dly high;
  59 } delay_range;
  60
  61 typedef struct vx900_delay_calib_st {
  62         delay_range rx_dq_cr;
  63         delay_range rx_dqs;
  64         /* Transmit delays are calibrated for each dimm */
  65         delay_range tx_dq[VX900_MAX_DIMM_SLOTS];
  66         delay_range tx_dqs[VX900_MAX_DIMM_SLOTS];
  67 } vx900_delay_calib;
  68
  69 typedef struct ramctr_timing_st {
  70         enum spd_memory_type dram_type;
  71         enum spd_dimm_type dimm_type;
  72         u16 cas_supported;
  73         /* tLatencies are in units of ns, scaled by x256 */
  74         u32 tCK;
  75         u32 tAA;
  76         u32 tWR;
  77         u32 tRCD;
  78         u32 tRRD;
  79         u32 tRP;
  80         u32 tRAS;
  81         u32 tRC;
  82         u32 tRFC;
  83         u32 tWTR;
  84         u32 tRTP;
  85         u32 tFAW;
  86         /* Latencies in terms of clock cycles
  87          * They are saved separately as they are needed for DRAM MRS commands*/
  88         u8 CAS; /* CAS read latency */
  89         u8 CWL; /* CAS write latency */
  90         u8 WR;  /* write recovery time */
  91         /* Number of dimms currently connected */
  92         u8 n_dimms;
  93
  94 } ramctr_timing;
  95
  96 void vx900_init_dram_ddr3(const dimm_layout *dimms);
  97
  98 #endif /* RAMINIT_VX900_H */