src/northbridge/via/vx800/final_setting.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 One Laptop per Child, Association, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 static const u8 RefreshCounter[7][2] = {
  17         //Non_256Mbit, 256Mbit
  18         {0xCA, 0xA8},           // DRAM400
  19         {0xCA, 0xA8},           // DRAM333
  20         {0xCA, 0x86},           // DRAM266
  21         {0xCA, 0x65},           // DRAM200
  22         {0xA8, 0x54},           // DRAM166
  23         {0x86, 0x43},           // DRAM133
  24         {0x65, 0x32}            // DRAM100
  25 };
  26
  27 void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr)
  28 {
  29         u8 Data;
  30         u8 Freq = 5, i, Dram_256_Mb;
  31         if (DramAttr->DramFreq == DIMMFREQ_800)
  32                 Freq = 0;
  33         else if (DramAttr->DramFreq == DIMMFREQ_667)
  34                 Freq = 1;
  35         else if (DramAttr->DramFreq == DIMMFREQ_533)
  36                 Freq = 2;
  37         else if (DramAttr->DramFreq == DIMMFREQ_400)
  38                 Freq = 3;
  39         else if (DramAttr->DramFreq == DIMMFREQ_333)
  40                 Freq = 4;
  41         else if (DramAttr->DramFreq == DIMMFREQ_266)
  42                 Freq = 5;
  43         else if (DramAttr->DramFreq == DIMMFREQ_200)
  44                 Freq = 6;
  45         else
  46                 Freq = 6;
  47
  48         Dram_256_Mb = 0;
  49         for (i = 0; i < MAX_SOCKETS; i++) {
  50                 if (DramAttr->DimmInfo[i].SPDDataBuf[SPD_SDRAM_ROW_ADDR] == 13) {
  51                         Dram_256_Mb = 1;
  52                         break;
  53                 }
  54         }
  55
  56         Data = RefreshCounter[Freq][Dram_256_Mb];
  57
  58         pci_write_config8(MEMCTRL, 0x6a, Data);
  59 }
  60
  61 /*===================================================================
  62 Function   : DRAMRegFinalValue()
  63 Precondition :
  64 Input      :
  65                    DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
  66                                     in MotherBoard
  67 Output     : Void
  68 Purpose   : Chipset Performance UP and other setting after DRAM Sizing
  69                  Turn on register directly to promote performance
  70 ===================================================================*/
  71
  72 //--------------------------------------------------------------------------
  73 //        register       AND   OR
  74 //--------------------------------------------------------------------------
  75 #define DRAM_table_item         9
  76 static const u8 DRAM_table[DRAM_table_item][3] = {
  77         {0x60, 0xff, 0xD0},
  78         {0x66, 0xcf, 0x80},     // DRAMC queue > 2
  79         {0x69, 0xff, 0x07},     // Enable multiple page
  80         {0x95, 0x00, 0x0D},
  81         {0x96, 0x0F, 0xA0},
  82         {0xFB, 0x00, 0x3E},
  83         {0xFD, 0x00, 0xA9},
  84         {0xFE, 0x00, 0x0f},
  85         {0xFF, 0x00, 0x3D}
  86 };
  87
  88 #define PM_table_item           5
  89 static const u8 PM_table[PM_table_item][3] = {
  90         {0xA0, 0x0F, 0xF0},
  91         {0xA1, 0x1F, 0xE0},
  92         {0xA2, 0x00, 0xFE},
  93         {0xA3, 0x7F, 0x80},
  94         {0xA5, 0x7E, 0x81},
  95 };
  96
  97 void DRAMRegFinalValue(DRAM_SYS_ATTR * DramAttr)
  98 {
  99         u8 Data;
 100         u8 i;
 101
 102         for (i = 0; i < DRAM_table_item; i++) {
 103                 Data = pci_read_config8(MEMCTRL, DRAM_table[i][0]);
 104                 Data = (u8) ((Data & DRAM_table[i][1]) | DRAM_table[i][2]);
 105                 pci_write_config8(MEMCTRL, DRAM_table[i][0], Data);
 106         }
 107
 108         //enable dram By-Rank self refresh
 109         Data = pci_read_config8(MEMCTRL, 0x96);
 110         Data &= 0xF0;
 111         for (i = 0x01; i < 0x10; i = i << 1) {
 112                 if ((DramAttr->RankPresentMap & i) != 0x00)
 113                         Data |= i;
 114         }
 115         pci_write_config8(MEMCTRL, 0x96, Data);
 116
 117         for (i = 0; i < PM_table_item; i++) {
 118                 Data = pci_read_config8(PCI_DEV(0, 0, 4), PM_table[i][0]);
 119                 Data = (u8) ((Data & PM_table[i][1]) | PM_table[i][2]);
 120                 pci_write_config8(PCI_DEV(0, 0, 4), PM_table[i][0], Data);
 121         }
 122
 123 }