src/northbridge/via/vx800/early_serial.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 One Laptop per Child, Association, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14 */
  15
  16 /*
  17  * Enable the serial devices on the VIA
  18  */
  19 #include <arch/io.h>
  20
  21 /* The base address is 0x15c, 0x2e, depending on config bytes */
  22
  23 #define SIO_BASE 0x3f0
  24 #define SIO_DATA  SIO_BASE+1
  25
  26 static void vx800_writepnpaddr(uint8_t val)
  27 {
  28         outb(val, 0x2e);
  29         outb(val, 0xeb);
  30 }
  31
  32 static void vx800_writepnpdata(uint8_t val)
  33 {
  34         outb(val, 0x2f);
  35         outb(val, 0xeb);
  36 }
  37
  38 static void vx800_writesiobyte(uint16_t reg, uint8_t val)
  39 {
  40         outb(val, reg);
  41 }
  42
  43 static void vx800_writesioword(uint16_t reg, uint16_t val)
  44 {
  45         outw(val, reg);
  46 }
  47
  48 /* regs we use: 85, and the southbridge devfn is defined by the
  49    mainboard
  50  */
  51
  52 void enable_vx800_serial(void)
  53 {
  54         post_code(0x06);
  55         outb(0x03, 0x22);
  56
  57         //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e);
  58         //pci_write_config8(PCI_DEV(0,17,0),0xb0,0x10);
  59
  60         // turn on pnp
  61         vx800_writepnpaddr(0x87);
  62         vx800_writepnpaddr(0x87);
  63         // now go ahead and set up com1.
  64         // set address
  65         vx800_writepnpaddr(0x7);
  66         vx800_writepnpdata(0x2);
  67         // enable serial out
  68         vx800_writepnpaddr(0x30);
  69         vx800_writepnpdata(0x1);
  70         // serial port 1 base address (FEh)
  71         vx800_writepnpaddr(0x60);
  72         vx800_writepnpdata(0xfe);
  73         // serial port 1 IRQ (04h)
  74         vx800_writepnpaddr(0x70);
  75         vx800_writepnpdata(0x4);
  76         // serial port 1 control
  77         vx800_writepnpaddr(0xf0);
  78         vx800_writepnpdata(0x2);
  79         // turn of pnp
  80         vx800_writepnpaddr(0xaa);
  81
  82         // set up reg to set baud rate.
  83         vx800_writesiobyte(0x3fb, 0x80);
  84         // Set 115 kb
  85         vx800_writesioword(0x3f8, 1);
  86         // Set 9.6 kb
  87         //      WRITESIOWORD(0x3f8, 12)
  88         // now set no parity, one stop, 8 bits
  89         vx800_writesiobyte(0x3fb, 3);
  90         // now turn on RTS, DRT
  91         vx800_writesiobyte(0x3fc, 3);
  92         // Enable interrupts
  93         vx800_writesiobyte(0x3f9, 0xf);
  94         // should be done. Dump a char for fun.
  95         vx800_writesiobyte(0x3f8, 48);
  96         post_code(0x07);
  97 }