src/northbridge/via/cx700/sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <device/device.h>
  18 #include <device/pci.h>
  19 #include <device/pci_ids.h>
  20
  21 /* IDE specific bits */
  22 #define IDE_MODE_REG            0x09
  23 #define IDE0_NATIVE_MODE        (1 << 0)
  24 #define IDE1_NATIVE_MODE        (1 << 2)
  25
  26 /* These are default addresses */
  27 #define IDE0_DATA_ADDR          0x1f0
  28 #define IDE0_CONTROL_ADDR       0x3f4
  29 #define IDE1_DATA_ADDR          0x170
  30 #define IDE1_CONTROL_ADDR       0x370
  31
  32 #define BUS_MASTER_ADDR         0xfc00
  33
  34 #define CHANNEL_ENABLE_REG      0x40
  35 #define ENABLE_IDE0             (1 << 0)
  36 #define ENABLE_IDE1             (1 << 1)
  37
  38 /* TODO: better user configuration */
  39 #define DISABLE_SATA 0
  40
  41 static void sata_init(struct device *dev)
  42 {
  43         u8 reg8;
  44
  45         printk(BIOS_DEBUG, "Configuring VIA SATA & EIDE Controller\n");
  46
  47         /* Class IDE Disk, instead of RAID controller */
  48         reg8 = pci_read_config8(dev, 0x45);
  49         reg8 &= 0x7f;           /* Sub Class Write Protect off */
  50         pci_write_config8(dev, 0x45, reg8);
  51         pci_write_config8(dev, 0x0a, 0x01);
  52         reg8 |= 0x80;           /* Sub Class Write Protect on */
  53         pci_write_config8(dev, 0x45, reg8);
  54
  55 #if defined(DISABLE_SATA) && (DISABLE_SATA == 1)
  56         printk(BIOS_INFO, "Disabling SATA (Primary Channel)\n");
  57         /* Disable SATA channels */
  58         pci_write_config8(dev, 0x40, 0x00);
  59 #else
  60         pci_write_config8(dev, 0x40, 0x43);
  61 #endif
  62
  63         reg8 = pci_read_config8(dev, 0x6a);
  64         reg8 |= 0x8;            /* Mode Select set to Manual Mode */
  65         reg8 &= ~7;
  66         reg8 |= 0x2;            /* Manual setting to 50 ohm */
  67
  68         pci_write_config8(dev, 0x6a, reg8);
  69
  70         reg8 = pci_read_config8(dev, 0x6b);
  71         reg8 &= ~7;
  72         reg8 |= 0x01;           /* Autocomp of Termination */
  73         pci_write_config8(dev, 0x6b, reg8);
  74
  75         /* Enable EIDE (secondary channel) even if SATA disabled */
  76         reg8 = pci_read_config8(dev, 0xc0);
  77         reg8 |= 0x1;
  78         pci_write_config8(dev, 0xc0, reg8);
  79
  80         // Enable bus mastering, memory space acces, io space access
  81         pci_write_config16(dev, 0x04, 0x0007);
  82
  83         /* Set SATA base ports. */
  84         pci_write_config32(dev, 0x10, 0x01f1);
  85         pci_write_config32(dev, 0x14, 0x03f5);
  86         /* Set EIDE base ports. */
  87         pci_write_config32(dev, 0x18, 0x0171);
  88         pci_write_config32(dev, 0x1c, 0x0375);
  89
  90         /* SATA/EIDE Bus Master mode base address */
  91         pci_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
  92
  93         /* Enable read/write prefetch buffers */
  94         reg8 = pci_read_config8(dev, 0xc1);
  95         reg8 |= 0x30;
  96         pci_write_config8(dev, 0xc1, reg8);
  97
  98         /* Set FIFO thresholds like */
  99         pci_write_config8(dev, 0xc3, 0x1);      /* FIFO flushed when 1/2 full */
 100
 101         /* EIDE Sector Size */
 102         pci_write_config16(dev, 0xe8, 0x200);
 103
 104         /* Some Miscellaneous Control */
 105         pci_write_config8(dev, 0x44, 0x7);
 106         pci_write_config8(dev, 0x45, 0xaf);
 107         pci_write_config8(dev, 0x46, 0x8);
 108
 109         /* EIDE Configuration */
 110         reg8 = pci_read_config8(dev, 0xc4);
 111         reg8 |= 0x10;
 112         pci_write_config8(dev, 0xc4, reg8);
 113
 114         pci_write_config8(dev, 0xc5, 0xc);
 115
 116         /* Interrupt Line */
 117         reg8 = pci_read_config8(dev, 0x45);
 118         reg8 &= ~(1 << 4);      /* Interrupt Line Write Protect off */
 119         pci_write_config8(dev, 0x45, reg8);
 120
 121         pci_write_config8(dev, 0x3c, 0x0e);     /* Interrupt */
 122
 123         /* Set the drive timing control */
 124         pci_write_config16(dev, 0x48, 0x5d5d);
 125
 126         /* Enable only compatibility mode. */
 127         reg8 = pci_read_config8(dev, 0x42);
 128         reg8 &= ~0xa0;
 129         pci_write_config8(dev, 0x42, reg8);
 130         reg8 = pci_read_config8(dev, 0x42);
 131         printk(BIOS_DEBUG, "Reg 0x42 read back as 0x%x\n", reg8);
 132
 133         /* Support Staggered Spin-Up */
 134         reg8 = pci_read_config8(dev, 0xb9);
 135         if ((reg8 & 0x8) == 0) {
 136                 printk(BIOS_DEBUG, "start OOB sequence on both drives\n");
 137                 reg8 |= 0x30;
 138                 pci_write_config8(dev, 0xb9, reg8);
 139         }
 140 }
 141
 142 static struct device_operations sata_ops = {
 143         .read_resources   = pci_dev_read_resources,
 144         .set_resources    = pci_dev_set_resources,
 145         .enable_resources = pci_dev_enable_resources,
 146         .init             = sata_init,
 147         .enable           = 0,
 148         .ops_pci          = 0,
 149 };
 150
 151 /* When the SATA controller is in IDE mode, the Device ID is 0x5324 */
 152 static const struct pci_driver northbridge_driver __pci_driver = {
 153         .ops = &sata_ops,
 154         .vendor = PCI_VENDOR_ID_VIA,
 155         .device = 0x5324,
 156 };