src/northbridge/via/cx700/early_smbus.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 // other bioses use this, too:
  17 #define SMBUS_IO_BASE           0x0500
  18
  19 #define SMBHSTSTAT              SMBUS_IO_BASE + 0x0
  20 #define SMBSLVSTAT              SMBUS_IO_BASE + 0x1
  21 #define SMBHSTCTL               SMBUS_IO_BASE + 0x2
  22 #define SMBHSTCMD               SMBUS_IO_BASE + 0x3
  23 #define SMBXMITADD              SMBUS_IO_BASE + 0x4
  24 #define SMBHSTDAT0              SMBUS_IO_BASE + 0x5
  25 #define SMBHSTDAT1              SMBUS_IO_BASE + 0x6
  26
  27 #define SMBBLKDAT               SMBUS_IO_BASE + 0x7
  28 #define SMBSLVCTL               SMBUS_IO_BASE + 0x8
  29 #define SMBTRNSADD              SMBUS_IO_BASE + 0x9
  30 #define SMBSLVDATA              SMBUS_IO_BASE + 0xa
  31 #define SMLINK_PIN_CTL          SMBUS_IO_BASE + 0xe
  32 #define SMBUS_PIN_CTL           SMBUS_IO_BASE + 0xf
  33
  34 /* Define register settings */
  35 #define HOST_RESET              0xff
  36 #define READ_CMD                0x01    // 1 in the 0 bit of SMBHSTADD states to READ
  37
  38 #define SMBUS_TIMEOUT           (100*1000*10)
  39
  40 #define I2C_TRANS_CMD           0x40
  41 #define CLOCK_SLAVE_ADDRESS     0x69
  42
  43 #define SMBUS_DELAY()           outb(0x80, 0x80)
  44
  45 /* Internal functions */
  46 #if CONFIG_DEBUG_SMBUS
  47 static void smbus_print_error(unsigned char host_status_register, int loops)
  48 {
  49         /* Check if there actually was an error */
  50         if (host_status_register == 0x00 || host_status_register == 0x40 ||
  51             host_status_register == 0x42)
  52                 return;
  53         printk(BIOS_ERR, "SMBus Error: %02x\n", host_status_register);
  54
  55         if (loops >= SMBUS_TIMEOUT) {
  56                 printk(BIOS_ERR, "SMBus Timout\n");
  57         }
  58         if (host_status_register & (1 << 4)) {
  59                 printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
  60         }
  61         if (host_status_register & (1 << 3)) {
  62                 printk(BIOS_ERR, "Bus Error\n");
  63         }
  64         if (host_status_register & (1 << 2)) {
  65                 printk(BIOS_ERR, "Device Error\n");
  66         }
  67         if (host_status_register & (1 << 1)) {
  68                 /* This isn't a real error... */
  69                 printk(BIOS_DEBUG, "Interrupt/SMI# was Successful Completion\n");
  70         }
  71         if (host_status_register & (1 << 0)) {
  72                 printk(BIOS_ERR, "Host Busy\n");
  73         }
  74 }
  75 #endif
  76
  77 static void smbus_wait_until_ready(void)
  78 {
  79         int loops;
  80
  81         loops = 0;
  82
  83         /* Yes, this is a mess, but it's the easiest way to do it */
  84         while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) {
  85                 SMBUS_DELAY();
  86                 ++loops;
  87         }
  88 #if CONFIG_DEBUG_SMBUS
  89         /* Some systems seem to have a flakey SMBus. No need to spew a lot of
  90          * errors on those, once we know that SMBus access is principally
  91          * working.
  92          */
  93         smbus_print_error(inb(SMBHSTSTAT), loops);
  94 #endif
  95 }
  96
  97 static void smbus_reset(void)
  98 {
  99         outb(HOST_RESET, SMBHSTSTAT);
 100 }
 101
 102 /* Public functions */
 103 static void set_ics_data(unsigned char dev, int data, char len)
 104 {
 105         //int i;
 106         smbus_reset();
 107         /* clear host data port */
 108         outb(0x00, SMBHSTDAT0);
 109         SMBUS_DELAY();
 110         smbus_wait_until_ready();
 111
 112         /* read to reset block transfer counter */
 113         inb(SMBHSTCTL);
 114
 115         /* fill blocktransfer array */
 116         if (dev == 0xd2) {
 117                 //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
 118                 outb(0x0d, SMBBLKDAT);
 119                 outb(0x00, SMBBLKDAT);
 120                 outb(0x3f, SMBBLKDAT);
 121                 outb(0xcd, SMBBLKDAT);
 122                 outb(0x7f, SMBBLKDAT);
 123                 outb(0xbf, SMBBLKDAT);
 124                 outb(0x1a, SMBBLKDAT);
 125                 outb(0x2a, SMBBLKDAT);
 126                 outb(0x01, SMBBLKDAT);
 127                 outb(0x0f, SMBBLKDAT);
 128                 outb(0x0b, SMBBLKDAT);
 129                 outb(0x80, SMBBLKDAT);
 130                 outb(0x8d, SMBBLKDAT);
 131                 outb(0x9b, SMBBLKDAT);
 132         } else {
 133                 //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff};
 134                 outb(0x08, SMBBLKDAT);
 135                 outb(0xff, SMBBLKDAT);
 136                 outb(0x3f, SMBBLKDAT);
 137                 outb(0x00, SMBBLKDAT);
 138                 outb(0x00, SMBBLKDAT);
 139                 outb(0xff, SMBBLKDAT);
 140                 outb(0xff, SMBBLKDAT);
 141                 outb(0xff, SMBBLKDAT);
 142                 outb(0xff, SMBBLKDAT);
 143         }
 144
 145         //for (i=0; i < len; i++)
 146         //      outb(data[i],SMBBLKDAT);
 147
 148         outb(dev, SMBXMITADD);
 149         outb(0, SMBHSTCMD);
 150         outb(len, SMBHSTDAT0);
 151         outb(0x74, SMBHSTCTL);
 152
 153         SMBUS_DELAY();
 154
 155         smbus_wait_until_ready();
 156
 157         smbus_reset();
 158
 159 }
 160
 161 static unsigned int get_spd_data(const struct mem_controller *ctrl, unsigned int dimm,
 162                                  unsigned int offset)
 163 {
 164         unsigned int val, addr;
 165
 166         smbus_reset();
 167
 168         /* clear host data port */
 169         outb(0x00, SMBHSTDAT0);
 170         SMBUS_DELAY();
 171         smbus_wait_until_ready();
 172
 173         /* Fetch the SMBus address of the SPD ROM from
 174          * the ctrl struct in romstage.c in case they are at
 175          * non-standard positions.
 176          * SMBus Address shifted by 1
 177          */
 178         addr = (ctrl->channel0[dimm]) << 1;
 179
 180         outb(addr | 0x1, SMBXMITADD);
 181         outb(offset, SMBHSTCMD);
 182         outb(0x48, SMBHSTCTL);
 183
 184         SMBUS_DELAY();
 185
 186         smbus_wait_until_ready();
 187
 188         val = inb(SMBHSTDAT0);
 189         smbus_reset();
 190         return val;
 191 }
 192
 193 static void enable_smbus(void)
 194 {
 195         device_t dev;
 196
 197         /* The CX700 ISA Bridge (0x1106, 0x8324) is hardcoded to this location,
 198          * no need to probe.
 199          */
 200         dev = PCI_DEV(0, 17, 0);
 201
 202         /* SMBus Clock Select: Divider fof 14.318MHz */
 203         pci_write_config8(dev, 0x94, 0x20);
 204
 205         /* SMBus I/O Base, enable SMBus */
 206         pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
 207
 208         /* SMBus Clock from 128K Source, Enable SMBus Host Controller */
 209         pci_write_config8(dev, 0xd2, 0x05);
 210
 211         /* Enable I/O decoding */
 212         pci_write_config16(dev, 0x04, 0x0003);
 213
 214         /* Setup clock chips */
 215         set_ics_data(0xd2, 0, 14);
 216         set_ics_data(0xd4, 0, 9);
 217 }
 218
 219 /* Debugging Function */
 220 #if CONFIG_DEBUG_SMBUS
 221 static void dump_spd_data(const struct mem_controller *ctrl)
 222 {
 223         int dimm, offset, regs;
 224         unsigned int val;
 225
 226         for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
 227                 printk(BIOS_DEBUG, "SPD Data for DIMM %02x\n", dimm);
 228
 229                 val = get_spd_data(ctrl, dimm, 0);
 230                 if (val == 0xff) {
 231                         regs = 256;
 232                 } else if (val == 0x80) {
 233                         regs = 128;
 234                 } else {
 235                         printk(BIOS_DEBUG, "No DIMM present\n");
 236                         regs = 0;
 237                 }
 238                 for (offset = 0; offset < regs; offset++) {
 239                         printk(BIOS_DEBUG, "  Offset %02x = 0x%02x\n",
 240                                 offset, get_spd_data(ctrl, dimm, offset));
 241                 }
 242         }
 243 }
 244 #else
 245 #define dump_spd_data(ctrl)
 246 #endif