src/northbridge/intel/sch/early_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009-2010 iWave Systems
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "sch.h"
  17 #include <southbridge/intel/sch/sch.h>
  18
  19 #if 0
  20 static void sch_set_mtrr(void)
  21 {
  22         msr_t msr;
  23         printk(BIOS_DEBUG, "1");
  24         msr.hi = 0x06060606;
  25         msr.lo = 0x06060606;
  26         wrmsr(0x250, msr);
  27         printk(BIOS_DEBUG, "2");
  28         msr.hi = 0x06060606;
  29         msr.lo = 0x06060606;
  30         wrmsr(0x258, msr);
  31         printk(BIOS_DEBUG, "3");
  32         msr.hi = 0x0;
  33         msr.lo = 0x0;
  34         wrmsr(0x259, msr);
  35         printk(BIOS_DEBUG, "4");
  36         msr.hi = 0x04040404;
  37         msr.lo = 0x04040404;
  38         wrmsr(0x268, msr);
  39         printk(BIOS_DEBUG, "5");
  40         msr.hi = 0x04040404;
  41         msr.lo = 0x04040404;
  42         wrmsr(0x269, msr);
  43         printk(BIOS_DEBUG, "6");
  44         msr.hi = 0x04040404;
  45         msr.lo = 0x04040404;
  46         wrmsr(0x26A, msr);
  47         printk(BIOS_DEBUG, "7");
  48         msr.hi = 0x04040404;
  49         msr.lo = 0x04040404;
  50         wrmsr(0x26B, msr);
  51         printk(BIOS_DEBUG, "8");
  52         msr.hi = 0x04040404;
  53         msr.lo = 0x04040404;
  54         wrmsr(0x26C, msr);
  55         printk(BIOS_DEBUG, "9");
  56         msr.hi = 0x05050505;
  57         msr.lo = 0x05050505;
  58         wrmsr(0x26D, msr);
  59         printk(BIOS_DEBUG, "10");
  60         msr.hi = 0x05050505;
  61         msr.lo = 0x05050505;
  62         wrmsr(0x26E, msr);
  63         printk(BIOS_DEBUG, "11");
  64         msr.hi = 0x05050505;
  65         msr.lo = 0x05050505;
  66         wrmsr(0x26f, msr);
  67         printk(BIOS_DEBUG, "12");
  68         msr.hi = 0x0;
  69         msr.lo = 0x6;
  70         wrmsr(0x202, msr);
  71         printk(BIOS_DEBUG, "13");
  72         msr.hi = 0x0;
  73         msr.lo = 0xC0000800;
  74         wrmsr(0x203, msr);
  75         printk(BIOS_DEBUG, "14");
  76         msr.hi = 0x0;
  77         msr.lo = 0x3FAF0000;
  78         wrmsr(0x204, msr);
  79         printk(BIOS_DEBUG, "15");
  80         msr.hi = 0x0;
  81         msr.lo = 0xFFFF0800;
  82         wrmsr(0x205, msr);
  83         printk(BIOS_DEBUG, "16");
  84         msr.hi = 0x0;
  85         msr.lo = 0x3FB00000;
  86         wrmsr(0x206, msr);
  87         printk(BIOS_DEBUG, "16");
  88         msr.hi = 0x0;
  89         msr.lo = 0xFFF00800;
  90         wrmsr(0x207, msr);
  91         printk(BIOS_DEBUG, "17");
  92         msr.hi = 0x0;
  93         msr.lo = 0x3FC00000;
  94         wrmsr(0x208, msr);
  95         printk(BIOS_DEBUG, "18");
  96         msr.hi = 0x0;
  97         msr.lo = 0xFFC00800;
  98         wrmsr(0x209, msr);
  99         printk(BIOS_DEBUG, "19");
 100         msr.hi = 0x0;
 101         msr.lo = 0x0;
 102         wrmsr(0x20A, msr);
 103         printk(BIOS_DEBUG, "20");
 104         msr.hi = 0x0;
 105         msr.lo = 0x0;
 106         wrmsr(0x20B, msr);
 107         printk(BIOS_DEBUG, "21");
 108         msr.hi = 0x0;
 109         msr.lo = 0x0;
 110         wrmsr(0x20a, msr);
 111         printk(BIOS_DEBUG, "22");
 112         msr.hi = 0x0;
 113         msr.lo = 0x0;
 114         wrmsr(0x20B, msr);
 115         printk(BIOS_DEBUG, "23");
 116         msr.hi = 0x0;
 117         msr.lo = 0x0;
 118         wrmsr(0x20c, msr);
 119         msr.hi = 0x0;
 120         msr.lo = 0x0;
 121         wrmsr(0x20d, msr);
 122         msr.hi = 0x0;
 123         msr.lo = 0x0;
 124         wrmsr(0x20E, msr);
 125         msr.hi = 0x0;
 126         msr.lo = 0x0;
 127         wrmsr(0x20F, msr);
 128         msr.hi = 0x0;
 129         msr.lo = 0XC00;
 130         wrmsr(0x2FF, msr);
 131         printk(BIOS_DEBUG, "end");
 132 }
 133 #endif
 134
 135 static void sch_detect_chipset(void)
 136 {
 137         u16 reg16;
 138         u8 reg8;
 139         printk(BIOS_INFO, "\n");
 140         reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), 0x2);
 141         switch (reg16) {
 142         case 0x8101:
 143                 printk(BIOS_INFO, "UL11L/US15L");
 144                 break;
 145         case 0x8100:
 146                 printk(BIOS_INFO, "US15W");
 147                 break;
 148         default:
 149                 /* Others reserved. */
 150                 printk(BIOS_INFO, "Unknown (%02x)", reg16);
 151         }
 152         printk(BIOS_INFO, " Chipset ");
 153
 154         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x8);
 155         switch (reg8) {
 156         case 3:
 157                 printk(BIOS_INFO, "Qual. Sample ES1, Stepping B1");
 158                 break;
 159         case 4:
 160                 printk(BIOS_INFO, "Qual. Sample ES2, Stepping C0");
 161                 break;
 162         case 5:
 163                 printk(BIOS_INFO, "Qual. Sample ES2-Prime, Stepping D0");
 164                 break;
 165         case 6:
 166                 printk(BIOS_INFO, "Qual. Sample QS, Stepping D1");
 167                 break;
 168         default:
 169                 /* Others reserved. */
 170                 printk(BIOS_INFO, "Unknown (%02x)", reg8);
 171         }
 172         printk(BIOS_INFO, "\n");
 173 }
 174
 175 static void sch_setup_non_standard_bars(void)
 176 {
 177         printk(BIOS_DEBUG, "Setting up ACPI PM1 block ");
 178         /* Address 0x1000 size 16B */
 179         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x48,
 180                            (0x80000000 | DEFAULT_PMBASE));
 181
 182         printk(BIOS_DEBUG, "Setting up ACPI P block ");
 183         /* Address 0x1010 size 16B */
 184         sch_port_access_write(4, 0x70, 4, 0x80001010);
 185
 186         /* SMBus address 0x1040 size 64B */
 187         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x40, 0x80001040);
 188
 189         /* GPIO address 0x1080 size 64B */
 190         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x44, 0x80001080);
 191
 192         /* GPE0 address 0x10C0 size 64B */
 193         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x4C, 0x800010C0);
 194
 195         sch_port_access_write(2, 4, 4, 0x3F703F76); /* FIXME: SMM Control */
 196
 197         /* Base of Stolen Memory Address 0x1080 size 64B */
 198         pci_write_config32(PCI_DEV(0, 0x02, 0), 0x5C, 0x3F800000);
 199
 200         sch_port_access_write(0, 0, 4, DEFAULT_PCIEXBAR | 1); /* pre-b1 */
 201         sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */
 202
 203         /* RCBA */
 204         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0,
 205                            ((uintptr_t)DEFAULT_RCBABASE | 1));
 206
 207         printk(BIOS_DEBUG, " done.\n");
 208 }
 209
 210 static void sch_early_initialization(void)
 211 {
 212         /* Print some chipset specific information. */
 213         sch_detect_chipset();
 214
 215         /* Setup all non standard BARs. */
 216         sch_setup_non_standard_bars();
 217 }